This research was supported by the Creative Materials Discovery Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (NRF-2017M3D1A1039288). Also, this research was supported by the Institute for Information and Communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (No.2017000709, Integrated approaches of physically unclonable cryptographic primitives using random lasers and optoelectronics).

CAUTION: Some chemicals (i.e., hydrofluoric acid, buffered oxide etchant, isopropyl alcohol, etc.) used in this protocol can be hazardous to health. Please consult all relevant material safety data sheets before any sample preparation takes place. Utilize appropriate personal protective equipment (e.g., lab coats, safety glasses, gloves) and engineering controls (e.g., wet station, fume hood) when handling etchants and solvents.
1. Si Doping and Isolation
NOTE: See Figure 1a - 1d.
<ol>
	<li>Prepare a doped SOI wafer by ion implantation with the conditions as follows: dopant-phosphorous/boron, energy of 80/50 keV, and a dose of 5 x 1015/3 x 1015 cm-3 for n+ and p+ doping, respectively. To recover a crystallinity of the wafer, anneal the sample at a temperature of 1,000 &#176;C for 120 min in a furnace after ion implantation. Prepare the doped samples by using the ion implantation process from the National NanoFab Center (NNFC) for high process stability and deep doping depth (Figure 1a).</li>
	<li>To remove the native oxide, dip the diced sample using a Teflon dipper in buffered oxide etchant (BOE) for 5 s and clean the diced sample sequentially with acetone, isopropyl alcohol (IPA), and deionized (DI) water.</li>
	<li>Form a photoresist (PR) pattern for the Si isolation (Figure 1b).
	<ol>
		<li>Spin coat positive PR on the sample at 4,000 rpm for 40 s and soft bake the coated sample at 90 &#176;C for 90 s. Expose the sample to UV light with a photolithography mask for 10 s.</li>
		<li>Immerse the sample in the developer for 1 min to define the pattern, clean it in DI water, and dry it with an N2 blowgun while holding it with forceps. Hard bake the sample for hardening the PR layer at 110 &#176;C for 5 min.</li>
	</ol>
	</li>
	<li>Dry etch the sample of Si using inductively coupled plasma-reactive ion etching (ICP-RIE) with 100 W RF power, 0 W ICP power, 30 mTorr chamber pressure, and SF6 gas (40 sccm) for 6 min (Figure 1c).</li>
	<li>To remove a buried oxide layer, dip the samples in hydrofluoric acid 49% for 2 min, using a Teflon dipper (Figure 1d).</li>
	<li>Clean the sample sequentially with acetone, IPA, and DI water. To remove the moisture, dry the sample with an N2 blowgun while holding it with forceps.</li>
</ol>
2. Sacrificial Oxide Layer Deposition
NOTE: See Figure 1e - 1g.
<ol>
	<li>Deposit a SiO2 sacrificial layer with a thickness of 130 nm using plasma enhanced chemical vapor deposition (PECVD) with a temperature of 230 &#176;C, 20 W RF power, 1000 mTorr pressure, SiH4 gas (100 sccm), and N2O gas (800 sccm) for 2 min (Figure 1e).</li>
	<li>Pattern the PR layer as a mask for a SiO2 sacrificial layer (Figure 1f).
	<ol>
		<li>Spin coat positive PR on the sample at 4,000 rpm for 40 s and soft bake the coated sample at 90 &#176;C for 90 s. Expose the sample to UV light with a photolithography mask for 10 s.</li>
		<li>Immerse the sample in the developer for 1 min to define the pattern, clean it in DI water, and dry it with N2 blowgun while holding it with forceps. Hard bake the sample for hardening the PR layer at 110 &#176;C for 5 min.</li>
	</ol>
	</li>
	<li>To pattern the PECVD oxide layer, dip the sample in BOE for 30 s, using a Teflon dipper (Figure 1g).</li>
	<li>Clean the sample sequentially with acetone, IPA, and DI water. To remove the moisture, dry the sample with an N2 blowgun while holding it with forceps.</li>
</ol>
3. Deposition of the First Layer of Polyimide and Performing the First Metallization
<ol>
	<li>Spin coat polyimide (PI) on the sample at 4,000 rpm for 60 s, anneal it at 110 &#176;C for 3 min and at 150 &#176;C for 10 min on a hot plate, and anneal it at 230 &#176;C for 60 min in an N2 atmosphere by supplying N2 to the oven (Figure 1h).</li>
	<li>Deposit a SiO2 layer with a thickness of 130 nm by using PECVD with a temperature of 230 &#176;C, 20 W RF power, 1,000 mTorr pressure, SiH4 gas (100 sccm), and N2O gas (800 sccm) for 2 min.</li>
	<li>Pattern the SiO2 as a hard mask layer for PI dry etching (Figure 1i).
	<ol>
		<li>Spin coat positive PR on the sample at 4,000 rpm for 40 s and soft bake the coated sample at 90 &#176;C for 90 s. Expose the sample to UV light with a photolithography mask for 10 s.</li>
		<li>Immerse the sample in the developer for 1 min to define the pattern, clean it in DI water, and dry it with an N2 blowgun while holding it with forceps. Hard bake the sample for hardening the PR layer at 110 &#176;C for 5 min.</li>
		<li>To pattern the SiO2 hard mask, dip the sample in BOE for 30 s using a Teflon dipper, clean it in DI water, and dry it with an N2 blowgun while holding it with forceps.</li>
	</ol>
	</li>
	<li>Dry etch the PI by using RIE with 30 W RF power, O2 gas (30 sccm), and Ar gas (70 sccm) for 20 min.</li>
	<li>To remove the PECVD oxide layer, dip the sample in BOE for 30 s, using a Teflon dipper.</li>
	<li>Clean the sample sequentially with acetone, IPA, and DI water. To remove the moisture, dry the sample with an N2 blowgun while holding it with forceps.</li>
	<li>Deposit 10 nm/200 nm thickness of Cr/Au by sputtering.</li>
	<li>Pattern the Cr/Au metal layer (Figure 1j).
	<ol>
		<li>Spin coat positive PR on the sample at 4,000 rpm for 40 s and soft bake the coated sample at 90 &#176;C for 90 s. Expose the sample to UV light with a photolithography mask for 10 s.</li>
		<li>Immerse the sample in the developer for 1 min to define the pattern, clean it in DI water, and dry it with an N2 blowgun while holding it with forceps. To harden the PR, hard bake the sample at 110 &#176;C for 5 min.</li>
		<li>Etch the Cr/Au layer with a wet etchant for 60 s/20 s, respectively.</li>
	</ol>
	</li>
	<li>Clean the sample sequentially with acetone, IPA, and DI water. To remove the moisture, dry the sample with an N2 blowgun while holding it with forceps. 
	NOTE: The cleaning process has to be very careful since there is a risk of peeling the PI layer.</li>
</ol>
4. Deposition of the Second Layer of Polyimide and Performing the Second Metallization
<ol>
	<li>Spin coat PI on the sample at 4,000 rpm for 60 s, anneal it at 110 &#176;C for 3 min and at 150 &#176;C for 10 min on a hot plate, and anneal it at 230 &#176;C for 60 min in an N2 atmosphere by supplying N2 to the oven (Figure 1k).</li>
	<li>Deposit a SiO2 layer with a thickness of 130 nm using PECVD with a temperature of 230 &#176;C, 20 W RF power, 1,000 mTorr pressure, SiH4 gas (100 sccm), and N2O gas (800 sccm) for 2 min.</li>
	<li>Pattern the SiO2 as a hard mask layer for dry etching (Figure 1l).
	<ol>
		<li>Spin coat positive PR on the sample at 4,000 rpm for 40 s and soft bake the coated sample at 90 &#176;C for 90 s. Expose the sample to UV light with a photolithography mask for 10 s.</li>
		<li>Immerse the sample in the developer for 1 min to define the pattern, clean it in DI water, and dry it with an N2 blowgun while holding it with forceps. Hard bake the sample for hardening the PR layer at 110 &#176;C for 5 min.</li>
		<li>To pattern the SiO2 hard mask, dip the sample in BOE for 30 s using a Teflon dipper, clean it in DI water, and dry it with an N2 blowgun while holding it with forceps.</li>
	</ol>
	</li>
	<li>Dry etch the PI using RIE with 30 W RF power, O2 gas (30 sccm), and Ar gas (70 sccm) for 50 min.</li>
	<li>To remove the PECVD oxide layer, dip the sample in BOE for 30 s, using a Teflon dipper.</li>
	<li>Clean the sample sequentially with acetone, IPA, and DI water.</li>
	<li>Deposit 10 nm/200 nm thickness of Cr/Au by sputter coating.</li>
	<li>Pattern the Cr/Au metal layer (Figure 1m).
	<ol>
		<li>Spin coat positive PR on the sample at 4,000 rpm for 40 s and soft bake the coated sample at 90 &#176;C for 90 s. Expose the sample to UV light with a photolithography mask for 10 s.</li>
		<li>Immerse the sample in the developer for 1 min to define the pattern, clean it in DI water, and dry it with an N2 blowgun while holding it with forceps. Hard bake the sample for hardening the PR layer at 110 &#176;C for 5 min.</li>
		<li>Etch the Cr/Au layer by a wet etchant for 60 s/20 s, respectively.</li>
	</ol>
	</li>
	<li>Clean the sample sequentially with acetone, IPA, and DI water.</li>
	<li>To remove the moisture, dry the clean substrate with a nitrogen blowgun while holding it with forceps. 
	NOTE: There is a risk of peeling the polyimide layer, so perform the cleaning process very carefully.</li>
</ol>
5. Encapsulating the Sample with PI and Opening Via Holes and Mesh Structure
<ol>
	<li>Spin coat PI on the sample at 4,000 rpm for 60 s, anneal it at 110 &#176;C for 3 min and at 150 &#176;C for 10 min on a hot plate, and anneal it at 230 &#176;C for 60 min in an N2 atmosphere by supplying N2 to the oven (Figure 1n).</li>
	<li>Deposit a SiO2 layer with a thickness of 650 nm using PECVD with a temperature of 230 &#176;C, 20 W RF power, 1,000 mTorr pressure, SiH4 gas (100 sccm), and N2O gas (800 sccm) for 8 min.</li>
	<li>Pattern the SiO2 as a hard mask layer for dry etching.
	<ol>
		<li>Spin coat positive PR on the sample at 4,000 rpm for 40 s and soft bake the coated sample at 90 &#176;C for 90 s. Expose the sample to UV light with a photolithography mask for 10 s.</li>
		<li>Immerse the sample in the developer for 2 min to define the pattern, clean it in DI water, and dry it with an N2 blowgun while holding it with forceps. Hard bake the sample for hardening the PR layer at 110 &#176;C for 5 min.</li>
		<li>To pattern the SiO2 hard mask, dip the sample in BOE for 1 min 30 s using a Teflon dipper, clean it in DI water, and dry it with an N2 blowgun while holding it with forceps. 
		NOTE: Due to the small size of the patterning, it is necessary to let it develop longer than the previous development time.</li>
	</ol>
	</li>
	<li>Dry etch the PI using RIE with 30 W RF power, O2 gas (30 sccm), and Ar gas (70 sccm) for 75 min.</li>
	<li>Dry etch the Si by ICP-RIE with 100 W RF power, 0 W ICP power, 30 mTorr chamber pressure, and 40 sccm SF6 gas for 6 min (Figure 1o).</li>
	<li>To remove the PECVD oxide layer, dip the sample in BOE for 1 min 30 s, using a Teflon dipper.</li>
	<li>Clean the sample sequentially with acetone, IPA, and DI water.</li>
	<li>Deposit a SiO2 layer with a thickness of 130 nm using PECVD with a temperature of 230 &#176;C, 20 W RF power, 1000 mTorr pressure, SiH4 gas (100 sccm), and N2O gas (800 sccm) for 2 min.</li>
	<li>Pattern the SiO2 as a hard mask layer for dry etching.
	<ol>
		<li>Spin coat positive PR on the sample at 4,000 rpm for 40 s and soft bake the coated sample at 90 &#176;C for 90 s. Expose the sample to UV light with a photolithography mask for 10 s.</li>
		<li>Immerse the sample in the developer for 1 min to define the pattern, clean it in DI water, and dry it with an N2 blowgun while holding it with forceps. Hard bake the sample for hardening the PR layer at 110 &#176;C for 5 min.</li>
		<li>To pattern the SiO2 hard mask, dip the sample in BOE for 1 min 30 s using a Teflon dipper, clean it in DI water, and dry it with an N2 blowgun while holding it with forceps.</li>
	</ol>
	</li>
	<li>Dry etch the PI by RIE with 30 W RF power, O2 gas (30 sccm), and Ar gas (70 sccm) for 75 min.</li>
	<li>To remove the PECVD oxide layer, dip the sample in BOE for 30 s, using a Teflon dipper.</li>
	<li>Clean the sample sequentially with acetone, IPA, and DI water. To remove the moisture, dry the clean sample with an N2 blowgun while holding it with forceps.</li>
</ol>
6. Etching the Sacrificial Layer and Transferring the Sample to Flexible Substrate
NOTE: See Figure 2.
<ol>
	<li>Etch the sacrificial layer by immersing the sample in hydrofluoric acid 49% for 20 min (Figure 2a; inset).</li>
	<li>Rinse the sample with DI water.</li>
	<li>After using the capillary phenomenon of a wiper to absorb the moisture between the substrate and the device, dry the clean sample with an N2 blowgun while holding it with forceps to remove the remaining moisture (Figure 2a).
	<ol>
		<li>Perform the process of rinsing and drying the sample. Due to the low adhesion between the device and the substrate, this has to be done very carefully, so as not to separate the substrate and the device.</li>
	</ol>
	</li>
	<li>Hold the sample using carbon tape and attach the water-soluble tape.</li>
	<li>Strip off the water-soluble tape in an instant to prevent the device from remaining on the substrate (Figure 2b).</li>
	<li>Confirm that the sample is attached to the water-soluble tape.</li>
	<li>Transfer the sample to a polydimethylsiloxane (PDMS) coated polyethylene terephthalate (PET) film (Figure 2c).
	<ol>
		<li>Prepare PDMS (10:1 mixture of prepolymer:curing agent) and remove any air bubbles in the PDMS by degassing.</li>
		<li>Spin coat the PDMS on the PET film at 1,000 rpm for 30 s and bake the PET film on a hot plate at a temperature of 110 &#176;C for 10 min.</li>
		<li>Expose the sample to UV light for 30 s to improve the adhesion of the PDMS and attach the water-soluble tape with the sample to the PDMS-coated PET film. 
		NOTE: UV treatment enhances the adhesion of a PDMS surface.</li>
	</ol>
	</li>
	<li>To remove the water-soluble tape, carefully drop water on it, using a pipette. Remove the water-soluble tape with a slow flow of water to prevent the device from being swept away by the water. Dry the sample slowly with an N2 blowgun while holding it with forceps (Figure 2d).</li>
</ol>

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N., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Ultra-thin+chip+technology+and+applications,+a+new+paradigm+in+silicon+technology.">Ultra-thin chip technology and applications, a new paradigm in silicon technology.</a> Solid-State Electronics. 54 (9), 818-829 (2010).</li><li>Shin, G., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Micromechanics+and+advanced+designs+for+curved+photodetector+arrays+in+hemispherical+electronic-eye+cameras.">Micromechanics and advanced designs for curved photodetector arrays in hemispherical electronic-eye cameras.</a> Small. 6 (7), 851-856 (2010).</li><li>Jung, I., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Paraboloid+electronic+eye+cameras+using+deformable+arrays+of+photodetectors+in+hexagonal+mesh+layouts.">Paraboloid electronic eye cameras using deformable arrays of photodetectors in hexagonal mesh layouts.</a> Applied Physics Letters. 96 (2), 21110 (2010).</li></ol>

The authors have nothing to disclose.

The fabrication technology described here contributes significantly to the progress of advanced electronics and wearable devices. The fundamental concepts of this approach use a thin Si membrane and metal interconnectors capable of stretching. Although Si is a brittle and hard material that can easily be fractured, a very thin Si layer can obtain a flexibility26,27. In the case of the metal interconnector, the wavy shape offers stretchability and flexibility<sup ...

Bio-inspired imaging systems can provide many advantages compared to the conventional imaging systems1,2,3,4,5. Retina or hemispherical ommatidia is a substantial component of biological visual system1,2,6. A curved image sensor, which mimics the critical element of animal eyes, can provide a compact and simple configuration of optical systems with low aberrations7. Diverse advancements of fabrication techniques and materials, for example, the use of intrinsically soft materials such as organic/nanomaterials8,9,10,11,12 and the introduction of deformable structures to semiconductors including silicon (Si) and germanium (Ge)1,2,3,13,14,15,16,17, realize the curved image sensors. Among them, Si-based approaches provide inherent advantages such as an abundance of material, mature technology, stability, and optical/electrical superiority. For this reason, although Si has intrinsic rigidity and brittleness, Si-based flexible electronics have been widely studied for various applications, such as flexible optoelectronics18,19,20 including curved image sensors1,2,3, and even wearable healthcare devices21,22.
In a recent study, we analyzed and improved the electrical performance of a thin Si photodetector array23. In that study, the optimum single unit cell of the curved photodetector array is a phototransistor (PTR) type that consists of a photodiode and blocking diode. The base junction gain amplifies a generated photocurrent, and hence it exhibits a route to improve an electrical performance with a thin film structure. In addition to the single cell, the thin film structure is suitable to suppress a dark current, which is considered as noise in the photodetector. Regarding doping concentration, a concentration larger than 1015 cm-3 is sufficient to achieve an exceptional performance in which the diode characteristics can be maintained with a light intensity over 10-3 W/cm2 23. Moreover, the PTR single cell has a low column noise and optically/electrically stable properties compared to that of the photodiode. Based on these design rules, we fabricated a flexible photodetector array that consists of thin Si PTRs using a silicon-on-insulator (SOI) wafer. In general, an important design rule of flexible image sensors is the neutral mechanical plane concept which defines the position through the thickness of the structure where strains are zero for an arbitrarily small r24. Another crucial point is a serpentine geometry of the electrode because a wavy shape provides fully reversible stretchability to the electrode. Due to these two important design concepts, the photodetector array can be flexible and stretchable. It facilitates the 3D deformation of the photodetector array into a hemispherical shape or a curved shape like the retina of animal eyes2.
In this work, we detail the processes for the fabrication of the curved PTR array using semiconductor fabrication processes (e.g., doping, etching, and deposition) and transfer printing. Also, we characterize a single PTR in terms of an I-V curve. In addition to the fabrication method and individual cell analysis, the electrical feature of the PTR array is analyzed in deformed states.

<table><tbody><tr><td>MBJ3</td><td>karl suss</td><td>MJB3 UV400 MASK ALIGNER</td><td>Mask aligner</td></tr><tr><td>80 plus RIE</td><td>Oxford instruments</td><td>Plasmalab 80 Plus for RIE</td><td>ICP-RIE</td></tr><tr><td>80 plus PECVD</td><td>Oxford instruments</td><td>Plasmalab 80 Plus forPECVD,</td><td>PECVD</td></tr><tr><td>SF-100ND</td><td>Rhabdos Co., Ltd.</td><td>SF-100ND</td><td>Spin coater</td></tr><tr><td>Polyimide</td><td>Sigma-Aldrich</td><td>575771</td><td>Poly(pyromellitic dianhydride-co-4,4&amp;prime;-oxydianiline), amic acid solution</td></tr><tr><td>SOI (silicon on insulator) wafer, 8inch</td><td>Soitec</td><td>SOI (silicon on insulator) wafer, 8inch</td><td>8inch SOI Wafer (silicon Thickness: 1.25&amp;mu;m)</td></tr><tr><td>Acetone</td><td>Duksan Pure Chemicals Co., Ltd.</td><td>3051</td><td>Acetone</td></tr><tr><td>Isopropyl Alcohol (IPA)</td><td>Duksan Pure Chemicals Co., Ltd.</td><td>4614</td><td>Isopropyl Alcohol (IPA)</td></tr><tr><td>Buffered Oxide Etch 6:1</td><td>Avantor</td><td>1278</td><td>Buffered Oxide Etch 6:1</td></tr><tr><td>HSD150-03P</td><td>Misung Scientific Co., Ltd</td><td>HSD150-03P</td><td>Hot plate</td></tr><tr><td>AZ5214</td><td>Microchemical</td><td>AZ5214</td><td>Photoresist</td></tr><tr><td>MIF300</td><td>Microchemical</td><td>MIF300</td><td>Developer</td></tr><tr><td>SYLGARD184</td><td>Dow Corning</td><td>SYLGARD184</td><td>Polydimethylsiloxane elastomer</td></tr><tr><td>Hydrofluoric Acid&amp;nbsp;</td><td>Duksan Pure Chemicals Co., Ltd.</td><td>2919</td><td>Hydrofluoric Acid&amp;nbsp;</td></tr><tr><td>CR-7</td><td>KMG Chemicals, Inc</td><td>210023</td><td>Chrome mask etchant</td></tr><tr><td>MFCD07370792</td><td>Sigma-Aldrich</td><td>651842</td><td>Gold etchant</td></tr></tbody></table>

fabrication of flexible image sensor based on lateral nipin phototransistors

Flexible photodetectors have been intensely studied for the use of curved image sensors, which are a crucial component in bio-inspired imaging systems, but several challenging points remain, such as a low absorption efficiency due to a thin active layer and low flexibility. We present an advanced method to fabricate a flexible phototransistor array with an improved electrical performance. The outstanding electrical performance is driven by a low dark current owing to deep impurity doping. Stretchable and flexible metal interconnectors simultaneously offer electrical and mechanical stabilities in a highly deformed state. The protocol explicitly describes the fabrication process of the phototransistor using a thin silicon membrane. By measuring I-V characteristics of the completed device in deformed states, we demonstrate that this approach improves the mechanical and electrical stabilities of the phototransistor array. We expect that this approach to a flexible phototransistor can be widely used for the applications of not only next-generation imaging systems/optoelectronics but also wearable devices such as tactile/pressure/temperature sensors and health monitors.

Figure 3a and 3b show the designed and fabricated structure of NIPIN PTR considering previous studies2,23. The inset in Figure 3a exhibits a basic I-V characteristic of PTR. The detailed structural parameters of PTR are shown in Figure 3b. The doping process for a Si layer on an SOI wafer was conducted using the ion implantat...

Watch this Scientific Journal Video about Fabrication of Flexible Image Sensor Based on Lateral NIPIN Phototransistors at JoVE.com

Fabrication of Flexible Image Sensor Based on Lateral NIPIN Phototransistors

We present a detailed method to fabricate a deformable lateral NIPIN phototransistor array for curved image sensors. The phototransistor array with an open mesh form, which is composed of thin silicon islands and stretchable metal interconnectors, provides flexibility and stretchability. The parameter analyzer characterizes the electrical property of the fabricated phototransistor.

Flexible photodetectors have been intensely studied for the use of curved image sensors, which are a crucial component in bio-inspired imaging systems, ...

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Research

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Engineering

7.7K Views.  Gwangju Institute of Science and Technology. Presenteren we een gedetailleerde methode om een vervormbare laterale NIPIN fototransistor array voor gebogen beeldsensors. De fototransistor matrix met een open mesh-formulier, dat is samengesteld uit dunne silicium-eilanden en rekbare metalen interconnectoren, biedt flexibiliteit en rekbaarheid. De parameter analyzer kenmerkt de elektrische eigenschap van de gefabriceerde fototransistor.

Video: Fabrication of Flexible Image Sensor Based on Lateral NIPIN Phototransistors

Printing Fabrication of Bulk Heterojunction Solar Cells and In Situ Morphology Characterization

Polymer-based materials hold promise as low-cost, flexible efficient photovoltaic devices. Most laboratory efforts to achieve high performance devices have used devices prepared by spin coating, a process that is not amenable to large-scale fabrication. This mismatch in device fabrication makes it difficult to translate quantitative results obtained in the laboratory to the commercial level, making optimization difficult. Using a mini-slot die coater, this mismatch can be resolved by translating the commercial process to the laboratory and characterizing the structure formation in the active layer of the device in real time and in situ as films are coated onto a substrate. The evolution of the morphology was characterized under different conditions, allowing us to propose a mechanism by which the structures form and grow. This mini-slot die coater offers a simple, convenient, material efficient route by which the morphology in the active layer can be optimized under industrially relevant conditions. The goal of this protocol is to show experimental details of how a solar cell device is fabricated using a mini-slot die coater and technical details of running in situ structure characterization using the mini-slot die coater.

Printing Fabrication of Bulk Heterojunction Solar Cells and In Situ Morphology Characterization

Here, we present a protocol to fabricate organic thin film solar cells using a mini-slot die coater and related in-line structure characterizations using synchrotron scattering techniques.

Polymer-based materials hold promise as low-cost, flexible efficient photovoltaic devices. Most laboratory efforts to achieve high performance devices ...

Fabrication of Fully Solution Processed Inorganic Nanocrystal Photovoltaic Devices

We demonstrate a method for the preparation of fully solution processed inorganic solar cells from a spin and spray coating deposition of nanocrystal inks. For the photoactive absorber layer, colloidal CdTe and CdSe nanocrystals (3-5 nm) are synthesized using an inert hot injection technique and cleaned with precipitations to remove excess starting reagents. Similarly, gold nanocrystals (3-5 nm) are synthesized under ambient conditions and dissolved in organic solvents. In addition, precursor solutions for transparent conductive indium tin oxide (ITO) films are prepared from solutions of indium and tin salts paired with a reactive oxidizer. Layer-by-layer, these solutions are deposited onto a glass substrate following annealing (200-400 &#176;C) to build the nanocrystal solar cell (glass/ITO/CdSe/CdTe/Au). Pre-annealing ligand exchange is required for CdSe and CdTe nanocrystals where films are dipped in NH4Cl:methanol to replace long-chain native ligands with small inorganic Cl- anions. NH4Cl(s) was found to act as a catalyst for the sintering reaction (as a non-toxic alternative to the conventional CdCl2(s) treatment) leading to grain growth (136&#177;39 nm) during heating. The thickness and roughness of the prepared films are characterized with SEM and optical profilometry. FTIR is used to determine the degree of ligand exchange prior to sintering, and XRD is used to verify the crystallinity and phase of each material. UV/Vis spectra show high visible light transmission through the ITO layer and a red shift in the absorbance of the cadmium chalcogenide nanocrystals after thermal annealing. Current-voltage curves of completed devices are measured under simulated one sun illumination. Small differences in deposition techniques and reagents employed during ligand exchange have been shown to have a profound influence on the device properties. Here, we examine the effects of chemical (sintering and ligand exchange agents) and physical treatments (solution concentration, spray-pressure, annealing time and annealing temperature) on photovoltaic device performance.

This protocol describes the synthesis and solution deposition of inorganic nanocrystals layer by layer to produce thin film electronics on non-conductive surfaces. Solvent-stabilized inks can produce complete photovoltaic devices on glass substrates via spin and spray coating following post-deposition ligand exchange and sintering.

We demonstrate a method for the preparation of fully solution processed inorganic solar cells from a spin and spray coating deposition of nanocrystal ...

Fabrication and Testing of Photonic Thermometers

In recent years, a push for developing novel silicon photonic devices for telecommunications has generated a vast knowledge base that is now being leveraged for developing sophisticated photonic sensors. Silicon photonic sensors seek to exploit the strong confinement of light in nano-waveguides to transduce changes in physical state to changes in resonance frequency. In the case of thermometry, the thermo-optic coefficient, i.e., changes in refractive index due to temperature, causes the resonant frequency of the photonic device such as a Bragg grating to drift with temperature. We are developing a suite of photonic devices that leverage recent advances in telecom compatible light sources to fabricate cost-effective photonic temperature sensors, which can be deployed in a wide variety of settings ranging from controlled laboratory conditions, to the noisy environment of a factory floor or a residence. In this manuscript, we detail our protocol for the fabrication and testing of photonic thermometers.

We describe the process of fabrication and testing of photonic thermometers.

In recent years, a push for developing novel silicon photonic devices for telecommunications has generated a vast knowledge base that is now being ...

Chemistry

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D materials is still in nascent stages, scientists cannot fully rely on traditional semiconductor techniques for related research. Delicate processes from locating the materials to electrode definition need to be well controlled. In this article, a universal fabrication protocol required in manufacturing nanoscale electronics, such as 2D quasi-heterojunction bipolar transistors (Q-HBT), and 2D back-gated transistors are demonstrated. This protocol includes the determination of material position, electron beam lithography (EBL), metal electrode definition, et al. A step by step narrative of the fabrication procedures for these devices are also presented. Furthermore, results show that each of the fabricated devices has achieved high performance with high repeatability. This work reveals a comprehensive description of process flow for preparing 2D nano-electronics, enables the research groups to access this information, and pave the way toward future electronics.

The article aims to introduce a standard and reliable fabrication procedure for the development of future low dimensional nanoelectronics.

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D ...

Polymeric Microneedle Array Fabrication by Photolithography

This manuscript describes the fabrication of polymeric microneedle (MN) arrays by photolithography. It involves a simple mold-free process by using a photomask consisting of embedded micro-lenses. Embedded micro-lenses were found to influence MN geometry (sharpness). Robust MN arrays with tip diameters ranging between 41.5 &#181;m &#177; 8.4 &#181;m and 71.6 &#181;m &#177; 13.7 &#181;m, with two different lengths (1,336 &#181;m &#177; 193 &#181;m and 957 &#181;m &#177; 171 &#181;m) were fabricated. These MN arrays may provide potential applications in delivery of low molecular and macromolecular therapeutic agents through skin.

Here, we present a protocol describing a mold-free fabrication process of the polymeric microneedles by photolithography.

This manuscript describes the fabrication of polymeric microneedle (MN) arrays by photolithography. It involves a simple mold-free process by using a ...

Bioengineering

Hybrid Printing for the Fabrication of Smart Sensors

A method to combine additively manufactured substrates or foils and multilayer inkjet printing for the fabrication of sensor devices is presented. First, three substrates (acrylate, ceramics, and copper) are prepared. To determine the resulting material properties of these substrates, profilometer, contact angle, scanning electron microscope (SEM), and focused ion beam (FIB) measurements are done. The achievable printing resolution and suitable drop volume for each substrate are, then, found through the drop size tests. Then, layers of insulating and conductive ink are inkjet printed alternately to fabricate the target sensor structures. After each printing step, the respective layers are individually treated by photonic curing. The parameters used for the curing of each layer are adapted depending on the printed ink, as well as on the surface properties of the respective substrate. To confirm the resulting conductivity and to determine the quality of the printed surface, four-point probe and profilometer measurements are done. Finally, a measurement set-up and results achieved by such an all-printed sensor system are shown to demonstrate the achievable quality.

Here we present a protocol for the fabrication of inkjet-printed multilayer sensor structures on additively manufactured substrates and foil.

A method to combine additively manufactured substrates or foils and multilayer inkjet printing for the fabrication of sensor devices is presented. First, ...

Characterization of SiN Integrated Optical Phased Arrays on a Wafer-Scale Test Station

Optical phased arrays (OPAs) can produce low-divergence laser beams and can be used to control the emission angle electronically without the need for moving mechanical parts. This technology is particularly useful for beam steering applications. Here, we focus on OPAs integrated into SiN photonic circuits for a wavelength in the near infrared. A characterization method of such circuits is presented, which allows the output beam of integrated OPAs to be shaped and steered. Furthermore, using a wafer-scale characterization setup, several devices can easily be tested across multiple dies on a wafer. In this way, fabrication variations can be studied, and high-performance devices identified. Typical images of OPA beams are shown, including beams emitted from OPAs with and without a uniform waveguide length, and with varying numbers of channels. In addition, the evolution of output beams during the phase optimization process and beam steering in two dimensions is presented. Finally, a study of the variation in the beam divergence of identical devices is performed with respect to their position on the wafer.

Here, we describe the operation of a SiN integrated photonic circuit containing optical phased arrays. The circuits are used to emit low divergence laser beams in the near infrared and steer them in two dimensions.

Optical phased arrays (OPAs) can produce low-divergence laser beams and can be used to control the emission angle electronically without the need for ...

High-Contrast and Fast Photorheological Switching of a Twist-Bend Nematic Liquid Crystal

Smart viscoelastic materials that respond to specific stimuli are one of the most attractive classes of materials important to future technologies, such as on-demand switchable adhesion technologies, actuators, molecular clutches, and nano-/microscopic mass transporters. Recently it was found that through a special solid-liquid transition, rheological properties can exhibit significant changes, thus providing suitable smart viscoelastic materials. However, designing materials with such a property is complex, and forward and backward switching times are usually long. Therefore, it is important to explore new working mechanisms to realize solid-liquid transitions, shorten the switching time, and enhance the contrast of rheological properties during switching. Here, a light-induced crystal-liquid phase transition is observed, which is characterized by means of polarizing light microscopy (POM), photorheometry, photo-differential scanning calorimetry (photo-DSC), and X-ray diffraction (XRD). The light-induced crystal-liquid phase transition presents key features such as (1) fast switching of crystal-liquid phases for both forward and backward reactions and (2) a high contrast ratio of viscoelasticity. In the characterization, POM is advantageous in offering information on the spatial distribution of LC molecule orientations, determining the type of liquid crystalline phases appearing in the material, and studying the orientation of LCs. Photorheometry allows measurement of a material&#8217;s rheological properties under light stimuli and can reveal the photorheological switching properties of materials. Photo-DSC is a technique to investigate thermodynamic information of materials in darkness and under light irradiation. Lastly, XRD allows studying of microscopic structures of materials. The goal of this article is to clearly present how to prepare and measure the discussed properties of a photorheological material.

This protocol demonstrates the preparation of a photorheological material that exhibits a solid phase, various liquid crystalline phases, and an isotropic liquid phase by increasing temperature. Presented here are methods for measuring the structure-viscoelasticity relationship of the material.

Smart viscoelastic materials that respond to specific stimuli are one of the most attractive classes of materials important to future technologies, such ...

Fabrication and Testing of Miniature Automatic Photophoretic Trapping Rigs

This paper presents an automated, rapid-fab-compatible, photophoretic trap test rig to enable the democratization and crowdsourcing of volumetric display research. The rig can be constructed within 2 h using a laser cutter, 3-dimensional (3D) printer, and common hand tools. In its current form, the rig can be used to test the following critical parameters: particle type, trap type, numerical aperture, and airflow at a rate of approximately 250 samples per hour. With minor modification, the rig can be made to test an even larger set of parameters, such as laser power and laser wavelength, depending on the user's needs. The rig can use machine vision for automated data capture and analysis. The operation and construction of the test rig are described with concise, easy-to-follow steps. Results from a four-unit test rig 'farm' covering the power and particle type parameters are reported. This platform will broaden the scope and composition of optical trap display parameters and researchers through accessibility and democratization.

This work describes and characterizes the fabrication of miniature automatic photophoretic trapping rigs.

This paper presents an automated, rapid-fab-compatible, photophoretic trap test rig to enable the democratization and crowdsourcing of volumetric display ...

A Simple and Scalable Fabrication Method for Organic Electronic Devices on Textiles

Today, wearable electronics devices combine a large variety of functional, stretchable, and flexible technologies. However, in many cases, these devices cannot be worn under everyday conditions. Therefore, textiles are commonly considered the best substrate to accommodate electronic devices in wearable use. In this paper, we describe how to selectively pattern organic electroactive materials on textiles from a solution in an easy and scalable manner. This versatile deposition technique enables the fabrication of wearable organic electronic devices on clothes.

In this paper, we present a protocol to selectively deposit organic materials on textiles, which allows for the direct integration of organic electronic devices with wearables. The fabricated devices can be fully integrated in textiles, respecting their mechanical appearance and enabling sensing capabilities.

Today, wearable electronics devices combine a large variety of functional, stretchable, and flexible technologies. However, in many cases, these devices ...

Fabrication of Flexible Image Sensor Based on Lateral NIPIN Phototransistors

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