This work was supported by the National Science Council, Taiwan under contract No. MOST 105-2112-M-003-016-MY3. This work was also in part supported by the National Nano Device Laboratories and e-beam laboratory in electrical engineering of National Taiwan University.

1. 2D Quasi-heterojunction Transistors Fabrication Process
<ol>
	<li>Prepare commercial c-plane sapphire.
	<ol>
		<li>Wash the whole single-side polished sapphire (2-inch) with acetone.</li>
		<li>Rinse the sapphire substrate with isopropyl alcohol.</li>
	</ol>
	</li>
	<li>Grow MoS2 on sapphire substrate using CVD in a hot-wall furnace.
	<ol>
		<li>Place 0.6 g of molybdenum trioxide (MoO3) powder in a quartz boat located at the heating zone center of the furnace. Put the sapphire substrate downstream next to the quartz boat containing the MoO3 powder.</li>
		<li>Prepare sulfur (S) powder in a separate quartz boat at the upstream side of the furnace. Maintain its temperature at 190 &#176;C during the reaction.</li>
		<li>Use argon (Ar = 70 sccm, 40 Torr) gas flow to bring the S and MoO3 vapors to the sapphire substrate while heating the center zone to 750 &#176;C.</li>
		<li>Keep the heating zone, after reaching the desired growth temperature of 750 &#176;C, for 15 min and then naturally cool down the furnace to room temperature.</li>
	</ol>
	</li>
	<li>Perform EBL. 
	NOTE: A thin Au of about 5 nm was deposited by the sputtering for discharging during all EBL processes on sapphire substrate
	<ol>
		<li>Identify, using an optical microscope, an area where MoS2 monolayer flakes are observed, then design the stripe pattern layout for that specific area using a design software (AutoCAD).</li>
		<li>Spin-coat photoresist (PR), for example polymethyl methacrylate (PMMA) or P015, on top of the sample at 2000 rpm for 60 s (room temperature). Ensure that the PR has covered the entire sample after spin coating.</li>
		<li>Heat the sample (Soft Bake) at 100 &#176;C for 90 s in order to evaporate the solvents in the PR and enhance the adhesion.</li>
		<li>Convert the pattern layout in step 1.3.1 into a specific file (example: GDS file), and upload it in the EBL software.</li>
		<li>Determine the ideal dose of electron beam based on the width of the lines in the layout. 
		NOTE: For line width narrower than 1 &#181;m, the ideal dose of electron beam is 110 &#181;C/cm2; for 1 to 5 &#181;m line width, the dose is 100 &#181;C/cm2; and for line width wider than 5 &#181;m, the dose is 80 &#181;C/cm2.</li>
		<li>Start exposing the sample to electron beam.</li>
		<li>Apply post-exposure bake (PEB) on the sample after the exposure in order to reduce the standing wave effects. Heat the sample at 120 &#176;C for 90 s.</li>
		<li>Use tetramethylammonium hydroxide (TMAH) 2.38% as developer. Immerse the sample to TMAH for 80 s. Wash out the TMAH with 200 mL of deionized water for 10 s.</li>
		<li>Examine if the pattern is well developed by optical microscopy.</li>
		<li>Conduct hard bake to get rid of extra water in PR. Heat the sample at 110 &#176;C for 90 s.</li>
	</ol>
	</li>
	<li>Define the stripe structures using 50 W oxygen (O2) plasma etching (1st etching) for 30 s to 2 min and remove PR using 50 mL of acetone.</li>
	<li>Grow tungsten diselenide (WSe2) using CVD on the target location, which will result in a preferred growth of WSe2 layer between the already existing MoS2 stripes on the sapphire substrate.
	<ol>
		<li>Place 0.6 g of tungsten trioxide (WO3) powder in a quartz boat located at the heating zone center of the furnace. Put the sapphire substrate downstream next to the quartz boat containing the WO3 powder.</li>
		<li>Prepare selenium (Se) powder in a separate quartz boat at the upstream side of the furnace. Maintain its temperature at 260 &#176;C during the reaction.</li>
		<li>Use Ar/H2 (Ar = 90 sccm, H2 = 6 sccm, 20 Torr) gas flow to bring the Se and WO3 vapors to the sapphire substrate while heating the center zone to 925 &#176;C.</li>
		<li>Keep the heating zone, after reaching the desired growth temperature of 925 &#176;C, for 15 min and then naturally cool down the furnace to room temperature.</li>
	</ol>
	</li>
	<li>Fabricate the metal pad arrays and alignment marks.
	<ol>
		<li>Overlay the patterns of metal pad arrays and alignment the marks using photolithography patterning technique.</li>
		<li>Deposit 20 nm/60 nm Ti/Au using electron gun evaporator. 
		NOTE: Gold is used to avoid the oxidization of the metal pads.</li>
		<li>Prepare and submerge the sample to 100 mL of acetone to dissolve PR and perform lift-off. Shake and blow the acetone while monitoring the whole process via optical microscopy until the metal pads become apparent.</li>
	</ol>
	</li>
	<li>Perform another EBL process to overlay a ribbon shape pattern on top of the MoS2-WSe2 heterojunction.
	<ol>
		<li>Measure the coordinate displacement between the target locations in the MoS2-WSe2 heterojunction and the alignment marks using optical microscopy and design the ribbon-shape layout based on these measurements using a software (AutoCAD).</li>
		<li>Spin-coat PR, for example PMMA or P015, on top of the sample at 2000 rpm for 60 s (room temperature). Ensure that the PR has covered the entire sample after spin coating.</li>
		<li>Heat the sample (Soft Bake) at 100 &#176;C for 90 s in order to evaporate the solvents in the PR and enhance the adhesion.</li>
		<li>Convert the pattern layout in step 1.7.1 into a specific file (example: GDS file), and upload it in the EBL software.</li>
		<li>Determine the ideal dose of electron beam based on the width of the lines in the layout. 
		NOTE: For line width narrower than 1 &#181;m, the ideal dose of electron beam is 110 &#181;C/cm2; for 1 to 5 &#181;m line width, the dose is 100 &#181;C/cm2; and for line width wider than 5 &#181;m, the dose is 80 &#181;C/cm2.</li>
		<li>Set up the EBL machine such that the position of the alignment marks in the sapphire substrate matches its correspondence in the layout.</li>
		<li>Start exposing the sample to electron beam.</li>
		<li>Apply PEB on the sample after exposure in order to reduce the standing wave effects. Heat the sample at 120 &#176;C for 90 s.</li>
		<li>Use TMAH 2.38% as the developer. Immerse the sample to TMAH for 80 s. Wash out the TMAH with 200 mL deionized water for 10 s.</li>
		<li>Examine if the pattern is well developed by optical microscopy.</li>
		<li>Conduct hard bake to get rid of extra water in PR. Heat the sample at 110 &#176;C for 90 s.</li>
	</ol>
	</li>
	<li>Use O2 plasma etching (2nd etching) to define a ribbon-shaped lateral heterojunction, and remove PR by acetone.</li>
	<li>Perform the EBL process to overlay the pattern of the Ti/Au metal electrodes.
	<ol>
		<li>Measure the coordinate displacement between the target locations in the MoS2-WSe2 heterojunction and the alignment marks using optical microscopy and design the metal electrode layout based on these measurements using a software (AutoCAD).</li>
		<li>Spin-coat PR, for example PMMA or P015, on top of the sample at 2000 rpm for 60 s (room temperature). Ensure that the PR has covered the entire sample after spin coating.</li>
		<li>Heat the sample (Soft Bake) at 100 &#176;C for 90 s in order to evaporate the solvents in the PR and enhance the adhesion.</li>
		<li>Convert the pattern layout in step 1.9.1 into a specific file (example: GDS file), and upload it in the EBL software.</li>
		<li>Determine the ideal dose of electron beam based on the width of the metal lines in the layout. 
		NOTE: For metal line width narrower than 1 &#181;m, the ideal dose of electron beam is 110 &#181;C/cm2; for 1 to 5 &#181;m line width, the dose is 100 &#181;C/cm2; and for line width wider than 5 &#181;m, the dose is 80 &#181;C/cm2.</li>
		<li>Set up the EBL machine such that the positions of the alignment marks in the sapphire substrate matches its correspondence in the layout.</li>
		<li>Start exposing the sample to electron beam.</li>
		<li>Apply PEB on the sample after exposure in order to reduce the standing wave effects. Heat the sample at 120 &#176;C for 90 s.</li>
		<li>Use TMAH 2.38% as the developer. Immerse the sample to TMAH for 80 s. Wash out the TMAH with 200 mL deionized water for 10 s.</li>
		<li>Examine if the pattern is well developed by optical microscopy.</li>
		<li>Conduct hard bake to get rid of extra water in PR. Heat the sample at 110 &#176;C for 90 s.</li>
	</ol>
	</li>
	<li>Perform Ti/Au Metal Deposition and Lift-off
	<ol>
		<li>Deposit Ti/Au metal using electron gun evaporator with the thickness of less than 100 nm, otherwise, it will be difficult to remove the PR and the unwanted metal by lift-off.</li>
		<li>Prepare and submerge the sample to 100 mL of acetone to dissolve PR and perform lift-off. Shake and blow the acetone while monitoring the whole process via optical microscopy until there are only metal lines and pads left.</li>
	</ol>
	</li>
	<li>Perform the EBL process in step 1.9 but overlay the Pd/Au metal electrode&#39;s pattern instead of Ti/Au.</li>
	<li>Perform the metal deposition and lift-off process in step 1.10 but deposit Pd/Au instead of Ti/Au.</li>
</ol>
2. 2D Back-gated Transistors Fabrication Process
<ol>
	<li>Prepare back-gated Si/SiO2 substrates with alignment marks.
	<ol>
		<li>Prepare homemade or commercial SiO2/Si substrate.</li>
		<li>Use photolithography or EBL patterning techniques to define the alignment mark.</li>
		<li>Perform reactive ion etching (RIE) on the SiO2/Si substrate until the total depth of the target area reaches 1000 nm and remove the PR by O2 plasma to reveal the formed alignment marks.</li>
		<li>Overlay the patterns of metal pad arrays using photolithography patterning technique.</li>
		<li>Deposit 20 nm/60 nm Ti/Au using electron gun evaporator. 
		NOTE: Gold is used to avoid oxidization of the metal pads.</li>
		<li>Prepare and submerge the sample to 100 mL of acetone to dissolve PR and perform lift-off. Shake and blow the acetone while monitoring the whole process by optical microscopy until the metal pads become apparent.</li>
	</ol>
	</li>
	<li>Perform CVD of MoS2 on sapphire substrate in a hot-wall furnace.
	<ol>
		<li>Place 0.6 g of MoO3 powder in a quartz boat located at the heating zone center of the furnace. Put the sapphire substrate downstream next to the quartz boat containing the MoO3 powder.</li>
		<li>Prepare S powder in a separate quartz boat at the upstream side of the furnace. Maintain its temperature at 190 &#176;C during the reaction.</li>
		<li>Use argon (Ar = 70 sccm, 40 Torr) gas flow to bring the S and MoO3 vapors to the sapphire substrate while heating the center zone to 750 &#176;C.</li>
		<li>Keep the heating zone, after reaching the desired growth temperature of 750 &#176;C, for 15 min and then naturally cool down the furnace to room temperature.</li>
	</ol>
	</li>
	<li>Transfer MoS2 from the sapphire to the back-gated SiO2/Si substrate.
	<ol>
		<li>Spin coat PMMA with the spin speed of 3500 rpm for 30 s on top of the MoS2 film.</li>
		<li>Bake the MoS2/sapphire sample at 120 &#176;C for 3 min in order to strengthen the PMMA coating.</li>
		<li>Dip the MoS2/Sapphire sample into 50 mL of ammonia solution (14.5%) for around 30 min to 2 h to separate the MoS2 film from the sapphire substrate.</li>
		<li>Pick up the film and transfer it to the SiO2/Si substrate.</li>
		<li>Bake the MoS2/SiO2/Si sample in order to enhance the adhesion between the MoS2 and SiO2 layers. Heat the sample at 120 &#176;C for around 30 min to 1 h.</li>
		<li>Remove the PMMA by washing it with 30 mL of acetone for around 30 min to 2 h.</li>
		<li>Rinse the sample with isopropyl alcohol and use nitrogen to blow it dry.</li>
	</ol>
	</li>
	<li>Perform EBL. 
	NOTE: There is no thin Au deposited on SiO2/Si substrate during EBL process since Si is somehow conductive.
	<ol>
		<li>Measure the coordinate displacement between the target locations and the alignment marks using optical microscopy and, based on these measurements, design the pattern layout of the metal electrodes using a design software. 
		NOTE: Metal electrodes connect the target points in the MoS2 sample to the metal pads in the SiO2/Si substrate.</li>
		<li>Spin-coat PR, for example PMMA or P015, on top of the sample at 2000 rpm for 60 s (room temperature). Ensure that the PR has covered the entire sample.</li>
		<li>Heat the sample (Soft Bake) at 100 &#176;C for 90 s in order to evaporate the solvents in the PR and enhance the adhesion.</li>
		<li>Convert the pattern layout in step 2.4.1 into a specific file (example: GDS file), and upload it in the EBL software.</li>
		<li>Determine the ideal dose of electron beam based on the width of the metal lines in the layout. 
		NOTE: For metal line width narrower than 1 &#181;m, the ideal dose of electron beam is 110 &#181;C/cm2; for 1 to 5 &#181;m line width, the dose is 100 &#181;C/cm2; and for line width wider than 5 &#181;m, the dose is 80 &#181;C/cm2.</li>
		<li>Set up the EBL machine such that the position of the alignment marks in the Si/SiO2 substrate matches its correspondence in the layout.</li>
		<li>Start exposing the sample to electron beam.</li>
		<li>Apply PEB on the sample after the exposure in order to reduce the standing wave effects. Heat the sample at 120 &#176;C for 90 s.</li>
		<li>Use TMAH 2.38% as the developer. Immerse the sample to TMAH for 80 s. Wash out the TMAH with 200 mL of deionized water for 10 s.</li>
		<li>Examine if the pattern is well developed by optical microscopy.</li>
		<li>Conduct hard bake to get rid of extra water in PR. Heat the sample at 110 &#176;C for 90 s.</li>
	</ol>
	</li>
	<li>Perform Au Metal Deposition and Lift-off
	<ol>
		<li>Deposit Au metal using electron gun evaporator with the thickness of less than 100 nm, otherwise, it will be difficult to remove the PR and the unwanted metal by lift-off.</li>
		<li>Prepare and submerge the sample to 100 mL of acetone to dissolve PR and perform lift-off. Shake and blow the acetone while monitoring the process via optical microscopy until there are only metal lines and pads left.</li>
	</ol>
	</li>
</ol>

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The authors have nothing to disclose.

In this article, the detailed procedures of fabricating novel electronics based on 2D materials in nanometer scale are demonstrated. Since the sample preparation procedures of each application have differences with each other, the overlapped processes were treated as the protocol. Electron beam patterning combined with material location determination and metal electrode definition thus serves as the protocol here. Among the two types of devices mentioned, the whole process of 2D back-gated transistors starting at wet transferring single crystal MoS2 films onto SiO2/Si substrates and ending at metal lift-off were presented. The reason why focus is given on 2D back gated transistors is the urgent need of improved 2D materials-based field effect transistors (FETs). Therefore, important points related to its fabrication process will be emphasized in the following paragraphs.
There are some tricky points in every step of the experiments. Firstly, the precedence of material locating followed by the removal of PMMA is required to avoid unfavorable adsorption while exposing the MoS2 films to air. The adsorption is one of the causes of performance degradation. Consequently, baking the sample, with a duration that is supposed to be longer than 30 min, after the transfer is necessary. Otherwise, the film is easy to be peeled off when dissolving PMMA with acetone due to the poor attachment of the films and dielectric, which results in the disappearance of the flakes at target positions. The dose of electron beam is another critical factor for patterning. High electron beam dosage is not suitable for patterns with narrow spacing between electrodes due to the proximity effect. On the other hand, decreasing its dosage may lead to the inability to achieve the ideal pattern. Fine tuning of the parameters of electron beam therefore needs to be conducted. Basically, a thin metal is preferable for easier lift-off, and its ideal thickness depends on the application and the thickness of the photo resist. For the 2D transistor in this project, metal thickness below 100 nm is acceptable.
One limitation of the method is that manual operation is required, so it is only suitable for research purposes. Once wafer scale synthesis techniques of these materials become well-developed, traditional semiconductor technology can take over this approach. Also, a trade-off between getting a higher resolution and material quality exists when choosing between optical imaging and the alternative method using scanning electron microscope (SEM) in determining the material location. The optical imaging method used in this protocol provides micrometer scale precision for locating positions, while SEM is more precise but could induce damage in the material. Therefore, using optical imaging as proposed in the protocol is the most expedient by far.
Since years of research seeking for the best way to develop new materials is indispensable, laboratory scope manufacturing with hands-on experiments still occupies an important position. Surely, this method can serve not only for 2D materials but also for 1D and the undiscovered materials in future, broadening the possibilities of nanoscale electronics.

Since past decades, mankind has been experiencing rapid downscale in the size of transistors and, consequently, an exponential increase in the number of transistors in integrated circuits (ICs). This maintains the continuous progress of silicon-based complementary metal-oxide semiconductor (CMOS) technology1. Moreover, this current trend in the size and performance of fabricated devices are still on-track with Moore&#39;s law, which states that the number of transistors on electronic chips, as well as their performance, doubles roughly every two years2. CMOS transistors are present in most, if not all, of the electronic devices available in the market and thus making it an integral part of human lives. Due to this, there are continuous demands for improvements in chip size and performance which have been pushing the manufacturers to keep following the Moore&#39;s law track.
Unfortunately, Moore&#39;s law appears to be nearing its end due to the amount of heat generated as more silicon circuitry is squeezed into a small area2. This calls for new types of materials that can provide the same, if not better, performance as silicon and, at the same time, can be implemented in a relatively smaller scale. Recently, new promising materials have been subjects of many material science researches. Such materials as one-dimensional (1D) carbon nanotubes3,4,5,6,7, 2D graphene8,9,10,11,12, and transition metal dichalcogenides (TMDs)13,14,15,16,17,18, are good candidates that can be used as substitute for the silicon-based CMOS and continue the Moore&#39;s law track.
Fabrication of small-scale devices requires careful determination of the material&#39;s location to successfully proceed to the other fabrication techniques such as lithography and metal electrode definition. So, the method presented in this paper was designed to address this need. Compared to the traditional semiconductor fabrication techniques19, the approach presented in this paper is tailor-fitted to the development of small-scale devices which needs more attention in terms of finding the location of the material. The aim of this method is to reliably fabricate 2D nanomaterial devices, such as 2D back-gated transistors and Q-HBTs, using standard fabrication processes. This can serve as a platform for future nanodevice developments as it paves the way towards the production of future advanced nano-scale devices.
In the proceeding section, the fabrication processes for 2D materials-based devices namely, the Q-HBT and 2D back-gated transistor are discussed in detail. Electron beam patterning combined with material location determination and metal electrode definition comprises the protocol since they are required in both mentioned processes. Part 1 discusses the step-by-step fabrication process of Q-HBTs20; and part 2 demonstrates a universal approach to obtain chemical vapor deposition (CVD) molybdenum disulfide (MoS2) back-gated transistors from transfer to lift-off21, which has been completely shown in the article. The detailed process flow is illustrated in (Figure 1).

<table><tbody><tr><td>E-gun Evaporator</td><td>AST</td><td>PEVA 600I</td><td></td></tr><tr><td>Au slug, 99.99%</td><td>Well-Being Enterprise Co</td><td>N/A</td><td></td></tr><tr><td>Ti slug, 99.99%</td><td>Well-Being Enterprise Co</td><td>N/A</td><td></td></tr><tr><td>E-beam Lithography System</td><td>Elionix</td><td>ELS7500-EX</td><td></td></tr><tr><td>Cold Wall CVD System</td><td>Sulfur Science</td><td>SCW600S</td><td></td></tr><tr><td>C-plane Sapphire substrate</td><td>Summit-Tech</td><td>X171999</td><td>(0001) &amp;plusmn; 0.2 &amp;deg; one side polished</td></tr><tr><td>100 nm SiO&lt;sub&gt;2&lt;/sub&gt;/Si</td><td></td><td></td><td>Fabricated in NDL</td></tr><tr><td>Ammonia Solution</td><td>BASF</td><td>Ammonia Solution 28% Selectipur</td><td></td></tr><tr><td>Molybdenum (Mo), 99.95%</td><td>Summit-Tech</td><td>N/A</td><td></td></tr><tr><td>Tungsten (W), 99.95%</td><td>Summit-Tech</td><td>N/A</td><td></td></tr><tr><td>Sulfur (S), 99.5%</td><td>Sigma-Aldrich</td><td>13803</td><td></td></tr><tr><td>Polymethyl Methacrylate (PMMA)</td><td>Microchem</td><td>8110788</td><td>Use for transfer process</td></tr><tr><td>Spin Coater</td><td>Laurell</td><td>WS 400B 6NPP LITE</td><td></td></tr><tr><td>Acetone</td><td>BASF</td><td>Acetone EL Selectipur</td><td></td></tr><tr><td>Isopropanol (IPA)</td><td>BASF</td><td>2-Propanol UPS</td><td></td></tr><tr><td>Photo Resist for EBL</td><td>TOK</td><td>TDUR-P-015</td><td></td></tr><tr><td>Plasma Cleaner</td><td>Harrick Plasma</td><td>PDC-32G</td><td>Oxygen plasma</td></tr></tbody></table>

a standard and reliable method to fabricate two-dimensional nanoelectronics

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D materials is still in nascent stages, scientists cannot fully rely on traditional semiconductor techniques for related research. Delicate processes from locating the materials to electrode definition need to be well controlled. In this article, a universal fabrication protocol required in manufacturing nanoscale electronics, such as 2D quasi-heterojunction bipolar transistors (Q-HBT), and 2D back-gated transistors are demonstrated. This protocol includes the determination of material position, electron beam lithography (EBL), metal electrode definition, et al. A step by step narrative of the fabrication procedures for these devices are also presented. Furthermore, results show that each of the fabricated devices has achieved high performance with high repeatability. This work reveals a comprehensive description of process flow for preparing 2D nano-electronics, enables the research groups to access this information, and pave the way toward future electronics.

The device fabrication processes have been applied to several of the corresponding author&#39;s researches involving the development of 2D material devices. In this part, the results of some of these researches are presented to demonstrate the effectivity of the protocol discussed above. A monolayer of lateral WSe2-MoS2 Q-HBT20 is selected as the first example. Using the standard device fabrication processes detailed in the protocol, the monolayer lateral WSe2-MoS2 heterojunctions were grown (Figure 2a) and then proceeded by the formation of the Q-HBT. Metal contacts were deposited on top of the lateral heterojunction to complete the Q-HBT. Ti/Au were deposited on top of the MoS2 layer (Figure 2c), followed by the deposition of Pd/Au on top of the WSe2 layer (Figure 2d). Several lateral Q-HBT were developed, such as the one with an n-p-n-p lateral heterojunction illustrated in (Figure 2d, 2e). The function of the Q-HBT device was verified by looking into its characteristic curves such as its output (IC-VCE) curve at common-emitter configuration (Figure 2f). Figure 2f shows that the lateral n-p-n Q-HBT works under two operating modes - the saturation mode and the active mode - which proves that the Q-HBT that was built using the fabrication process, indeed, functions as a transistor.
The process was also used to build 2D back-gated devices for MoS2 piezotronic strain/force sensor21 application. High-quality triangular monolayer MoS2 films were first synthesized using CVD in a sapphire substrate and then transferred into a Si/SiO2 substrate. The rest of the process of making the MoS2 film into a piezotronic device is discussed in the protocol section. Figure 3a shows an atomic force microscopy (AFM) image of a completed device consisting of a triangular MoS2 monolayer and several sets of source/drain (S-D) Au electrodes. To study the piezoelectric polarization direction, multiple contact electrodes around the triangle shape were intentionally designed. Figure 3b presents the schematic diagram of the piezotronic sensor device and the setup showing how a mechanical load is applied by an AFM tip to test its piezoelectric effect. Results in Figure 3c show that the sensor device&#39;s current flowing through one of its S-D electrode pairs decreases for every increase in applied force and vice versa, which is an expected behavior for a piezo sensor. Furthermore, the data in Figure 3d implies that the developed sensor is stable since a repeating application of applied force/strain barely changed its output current or response.
<img alt="Figure 1" class="xfigimg" src="/files/ftp_upload/57885/57885fig1.jpg" /> 
Figure 1. Schematic process flow of 2D electronic devices. The blue arrows represent the fabrication process flow of Q-HBT and brown for 2D back-gated transistor. Inset: (a) the 2D material on sapphire substrate coated with PMMA; (b) a sample heated while soaked in ammonia solution; (c) schematic diagram of a 2D material after metal deposition and lift-off process. <a href="https://www-jove-com.remotexs.ntu.edu.sg/files/ftp_upload/57885/57885fig1large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 2" class="xfigimg" src="/files/ftp_upload/57885/57885fig2.jpg" /> 
Figure 2. Two-dimensional lateral Q-HBT. (a). Phase image of AFM. The phase image shows clear contrast between WSe2 and MoS2. (b). The optical micrograph of a lateral heterostructure ribbon where n-type material is MoS2 and p-type material is WSe2. (c). The optical micrograph of the metal Ti/Au deposited on top of MoS2 in the lateral heterostructure ribbon. Note that this image has the same scale as in (d). (d). The optical micrograph of the lateral Q-HBT, showing an n&#8722;p&#8722;n&#8722;p lateral heterojunction. Black dashed box marks the position of the lateral heterostructure ribbon. (e). Schematic plot of a 2D Q-HBT. The yellow ribbons are MoS2 monolayers and the red ribbon is WSe2 monolayer. Ti/Au metal layers are designed to deposit on MoS2 while Pd/Au contacts with WSe2. (f). The output characteristics of the lateral n&#8722;p&#8722;n Q-HBT at different VBE values. Reprinted with permission from Blaschke, B. M., et al.10. <a href="https://www-jove-com.remotexs.ntu.edu.sg/files/ftp_upload/57885/57885fig2large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>
<img alt="Figure 3" class="xfigimg" src="/files/ftp_upload/57885/57885fig3.jpg" /> 
Figure 3. The MoS2 monolayer device. (a). AFM image of the MoS2 monolayer device. (b). Schematic illustration of a MoS2 device showing how a mechanical load is applied by an AFM tip to test its piezoelectric effect. (c).&#160;I-Vb characteristics of the MoS2 device at different applied forces under compressive strain when applying forces at locations denoted in upper inset resulting in compressive strain as shown schematically in lower insets. (d). Current response of CVD monolayer MoS2 device at repeated compressive strains at a fixed bias voltage of 1 V. Reprinted with permission from Lan, Y. W., et al.8.&#160;<a href="https://www-jove-com.remotexs.ntu.edu.sg/files/ftp_upload/57885/57885fig3large.jpg" target="_blank">Please click here to view a larger version of this figure.</a>

Watch this Scientific Journal Video about A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics at JoVE.com

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

The article aims to introduce a standard and reliable fabrication procedure for the development of future low dimensional nanoelectronics.

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D ...

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Nanyang Technological University

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9.5K Views.  National Taiwan Normal University. The article aims to introduce a standard and reliable fabrication procedure for the development of future low dimensional nanoelectronics. 

Video: A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Fabricating Nanogaps by Nanoskiving

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two electrodes-and generating them in practical quantities-is still challenging. The preparation of nanogap electrodes using nanoskiving, which is a form of edge lithography, is a fast, simple and powerful technique. This method is an entirely mechanical process which does not include any photo- or electron-beam lithographic steps and does not require any special equipment or infrastructure such as clean rooms. Nanoskiving is used to fabricate electrically addressable nanogaps with control over all three dimensions; the smallest dimension of these structures is defined by the thickness of the sacrificial layer (Al or Ag) or self-assembled monolayers. These wires can be manually positioned by transporting them on drops of water and are directly electrically-addressable; no further lithography is required to connect them to an electrometer.

The fabrication of electrically addressable, high-aspect-ratio (> 1000:1) metal nanowires separated by gaps of single nanometers using either sacrificial layers of aluminum and silver or self-assembled monolayers as templates is described. These nanogap structures are fabricated without a clean room or any photo- or electron-beam lithographic processes by a form of edge lithography known as nanoskiving.

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two ...

Chemistry

A Method to Fabricate Disconnected Silver Nanostructures in 3D

The standard nanofabrication toolkit includes techniques primarily aimed at creating 2D patterns in dielectric media. Creating metal patterns on a submicron scale requires a combination of nanofabrication tools and several material processing steps. For example, steps to create planar metal structures using ultraviolet photolithography and electron-beam lithography can include sample exposure, sample development, metal deposition, and metal liftoff. To create 3D metal structures, the sequence is repeated multiple times. The complexity and difficulty of stacking and aligning multiple layers limits practical implementations of 3D metal structuring using standard nanofabrication tools. Femtosecond-laser direct-writing has emerged as a pre-eminent technique for 3D nanofabrication.1,2 Femtosecond lasers are frequently used to create 3D patterns in polymers and glasses.3-7 However, 3D metal direct-writing remains a challenge. Here, we describe a method to fabricate silver nanostructures embedded inside a polymer matrix using a femtosecond laser centered at 800 nm. The method enables the fabrication of patterns not feasible using other techniques, such as 3D arrays of disconnected silver voxels.8 Disconnected 3D metal patterns are useful for metamaterials where unit cells are not in contact with each other,9 such as coupled metal dot10,11or coupled metal rod12,13 resonators. Potential applications include negative index metamaterials, invisibility cloaks, and perfect lenses.
In femtosecond-laser direct-writing, the laser wavelength is chosen such that photons are not linearly absorbed in the target medium. When the laser pulse duration is compressed to the femtosecond time scale and the radiation is tightly focused inside the target, the extremely high intensity induces nonlinear absorption. Multiple photons are absorbed simultaneously to cause electronic transitions that lead to material modification within the focused region. Using this approach, one can form structures in the bulk of a material rather than on its surface.
Most work on 3D direct metal writing has focused on creating self-supported metal structures.14-16 The method described here yields sub-micrometer silver structures that do not need to be self-supported because they are embedded inside a matrix. A doped polymer matrix is prepared using a mixture of silver nitrate (AgNO3), polyvinylpyrrolidone (PVP) and water (H2O). Samples are then patterned by irradiation with an 11-MHz femtosecond laser producing 50-fs pulses. During irradiation, photoreduction of silver ions is induced through nonlinear absorption, creating an aggregate of silver nanoparticles in the focal region. Using this approach we create silver patterns embedded in a doped PVP matrix. Adding 3D translation of the sample extends the patterning to three dimensions.

Femtosecond-laser direct-writing is frequently used to create three-dimensional (3D) patterns in polymers and glasses. However, patterning metals in 3D remains a challenge. We describe a method for fabricating silver nanostructures embedded inside a polymer matrix using a femtosecond laser centered at 800 nm.

The standard nanofabrication toolkit includes  techniques primarily aimed at creating 2D patterns in dielectric media. Creating  metal patterns on a ...

Nanomoulding of Functional Materials, a Versatile Complementary Pattern Replication Method to Nanoimprinting

We describe a nanomoulding technique which allows low-cost nanoscale patterning of functional materials, materials stacks and full devices. Nanomoulding combined with layer transfer enables the replication of arbitrary surface patterns from a master structure onto the functional material. Nanomoulding can be performed on any nanoimprinting setup and can be applied to a wide range of materials and deposition processes. In particular we demonstrate the fabrication of patterned transparent zinc oxide electrodes for light trapping applications in solar cells.

We describe a nanomoulding technique which allows low-cost nanoscale patterning of functional materials, materials stacks and full devices. Nanomoulding can be performed on any nanoimprinting setup and can be applied to a wide range of materials and deposition processes.

We describe a nanomoulding technique which  allows low-cost nanoscale patterning of functional materials, materials stacks  and full devices. Nanomoulding ...

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

A quantum computer is a computer composed of quantum bits (qubits) that takes advantage of quantum effects, such as superposition of states and entanglement, to solve certain problems exponentially faster than with the best known algorithms on a classical computer. Gate-defined lateral quantum dots on GaAs/AlGaAs are one of many avenues explored for the implementation of a qubit. When properly fabricated, such a device is able to trap a small number of electrons in a certain region of space. The spin states of these electrons can then be used to implement the logical 0 and 1 of the quantum bit. Given the nanometer scale of these quantum dots, cleanroom facilities offering specialized equipment- such as scanning electron microscopes and e-beam evaporators- are required for their fabrication. Great care must be taken throughout the fabrication process to maintain cleanliness of the sample surface and to avoid damaging the fragile gates of the structure. This paper presents the detailed fabrication protocol of gate-defined lateral quantum dots from the wafer to a working device. Characterization methods and representative results are also briefly discussed. Although this paper concentrates on double quantum dots, the fabrication process remains the same for single or triple dots or even arrays of quantum dots. Moreover, the protocol can be adapted to fabricate lateral quantum dots on other substrates, such as Si/SiGe.

This paper presents a detailed fabrication protocol for gate-defined semiconductor lateral quantum dots on gallium arsenide heterostructures. These nanoscale devices are used to trap few electrons for use as quantum bits in quantum information processing or for other mesoscopic experiments such as coherent conductance measurements.

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Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data.
Exceptionally flat, 5 cm diameter, 375 &#181;m thick Si wafers with about 1 &#181;m variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 &#176;C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

A method for permanently bonding two silicon wafers so as to realize a uniform enclosure is described. This includes wafer preparation, cleaning, RT bonding, and annealing processes. The resulting bonded wafers (cells) have uniformity of enclosure ~1%1,2. The resulting geometry allows for measurements of confined liquids and gasses.

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned ...

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by quantum mechanical effects such as tunneling through single dopants, scattering via interface defects, and discrete trap charge states. However, progress in silicon technology has shown that these phenomena can be harnessed and exploited for a new class of quantum-based electronics. Among others, multi-layer-gated silicon metal-oxide-semiconductor (MOS) technology can be used to control single charge or spin confined in electrostatically-defined quantum dots (QD). These QD-based devices are an excellent platform for quantum computing applications and, recently, it has been demonstrated that they can also be used as single-electron pumps, which are accurate sources of quantized current for metrological purposes. Here, we discuss in detail the fabrication protocol for silicon MOS QDs which is relevant to both quantum computing and quantum metrology applications. Moreover, we describe characterization methods to test the integrity of the devices after fabrication. Finally, we give a brief description of the measurement set-up used for charge pumping experiments and show representative results of electric current quantization.

The fabrication process and experimental characterization techniques relevant to single-electron pumps based on silicon metal-oxide-semiconductor quantum dots are discussed.

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Atomically Traceable Nanostructure Fabrication

Reducing the scale of etched nanostructures below the 10 nm range eventually will require an atomic scale understanding of the entire fabrication process being used in order to maintain exquisite control over both feature size and feature density. Here, we demonstrate a method for tracking atomically resolved and controlled structures from initial template definition through final nanostructure metrology, opening up a pathway for top-down atomic control over nanofabrication. Hydrogen depassivation lithography is the first step of the nanoscale fabrication process followed by selective atomic layer deposition of up to 2.8 nm of titania to make a nanoscale etch mask. Contrast with the background is shown, indicating different mechanisms for growth on the desired patterns and on the H passivated background. The patterns are then transferred into the bulk using reactive ion etching to form 20 nm tall nanostructures with linewidths down to ~6 nm. To illustrate the limitations of this process, arrays of holes and lines are fabricated. The various nanofabrication process steps are performed at disparate locations, so process integration is discussed. Related issues are discussed including using fiducial marks for finding nanostructures on a macroscopic sample and protecting the chemically reactive patterned Si(100)-H surface against degradation due to atmospheric exposure.

We report a protocol for combining the atomic metrology of the Scanning Tunneling Microscope for surface patterning with selective Atomic Layer Deposition and Reactive Ion Etching. Using a robust process involving numerous atmospheric exposures and transport, 3D nanostructures with atomic metrology are fabricated.

Reducing the scale of etched nanostructures below the 10 nm range eventually will require an atomic scale understanding of the entire fabrication process ...

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-&#954; dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive ...

Fabrication of Nanopillar-Based Split Ring Resonators for Displacement Current Mediated Resonances in Terahertz Metamaterials

Terahertz (THz) split ring resonator (SRR) metamaterials (MMs) has been studied for gas, chemical, and biomolecular sensing applications because the SRR is not affected by environmental characteristics such as the temperature and pressure surrounding the resonator. Electromagnetic radiation in THz frequencies is biocompatible, which is a critical condition especially for the application of the biomolecular sensing. However, the quality factor (Q-factor) and frequency responses of traditional thin-film based split ring resonator (SRR) MMs are very low, which limits their sensitivities and selectivity as sensors. In this work, novel nanopillar-based SRR MMs, utilizing displacement current, are designed to enhance the Q-factor up to 450, which is around 45 times higher than that of traditional thin-film-based MMs. In addition to the enhanced Q-factor, the nanopillar-based MMs induce a larger frequency shifts (17 times compared to the shift obtained by the traditional thin-film based MMs). Because of the significantly enhanced Q-factors and frequency shifts as well as the property of biocompatible radiation, the THz nanopillar-based SRR are ideal MMs for the development of biomolecular sensors with high sensitivity and selectivity without inducing damage or distortion to biomaterials. A novel fabrication process has been demonstrated to build the nanopillar-based SRRs for displacement current mediated THz MMs. A two-step gold (Au) electroplating process and an atomic layer deposition (ALD) process are used to create sub-10 nm scale gaps between Au nanopillars. Since the ALD process is a conformal coating process, a uniform aluminum oxide (Al2O3) layer with nanometer-scale thickness can be achieved. By sequentially electroplating another Au thin film to fill the spaces between Al2O3 and Au, a close-packed Au-Al2O3-Au structure with nano-scale Al2O3 gaps can be fabricated. The size of the nano-gaps can be well defined by precisely controlling the deposition cycles of the ALD process, which has an accuracy of 0.1 nm.

A protocol for the design and fabrication of a novel nanopillar-based split ring resonator (SRR) is presented.

Terahertz (THz) split ring resonator (SRR) metamaterials (MMs) has been studied for gas, chemical, and biomolecular sensing applications because the SRR ...

Fabrication of Nanoheight Channels Incorporating Surface Acoustic Wave Actuation via Lithium Niobate for Acoustic Nanofluidics

Controlled nanoscale manipulation of fluids is known to be exceptionally difficult due to the dominance of surface and viscous forces. Megahertz-order surface acoustic wave (SAW) devices generate tremendous acceleration on their surface, up to 108 m/s2, in turn responsible for many of the observed effects that have come to define acoustofluidics: acoustic streaming and acoustic radiation forces. These effects have been used for particle, cell, and fluid manipulation at the microscale, although more recently SAW has been used to produce similar phenomena at the nanoscale through an entirely different set of mechanisms. Controllable nanoscale fluid manipulation offers a broad range of opportunities in ultrafast fluid pumping and biomacromolecule dynamics useful for physical and biological applications. Here, we demonstrate nanoscale-height channel fabrication via room-temperature lithium niobate (LN) bonding integrated with a SAW device. We describe the entire experimental process including nano-height channel fabrication via dry etching, plasma-activated bonding on lithium niobate, the appropriate optical setup for subsequent imaging, and SAW actuation. We show representative results for fluid capillary filling and fluid draining in a nanoscale channel induced by SAW. This procedure offers a practical protocol for nanoscale channel fabrication and integration with SAW devices useful to build upon for future nanofluidics applications.

We demonstrate fabrication of nanoheight channels with the integration of surface acoustic wave actuation devices upon lithium niobate for acoustic nanofluidics via liftoff photolithography, nano-depth reactive ion etching, and room-temperature plasma surface-activated multilayer bonding of single-crystal lithium niobate, a process similarly useful for bonding lithium niobate to oxides.

Controlled nanoscale manipulation of fluids is known to be exceptionally difficult due to the dominance of surface and viscous forces. Megahertz-order ...