The Authors would like to acknowledge the individuals in the Quantum Electronics and Photonics Division of the National Institute of Standards and Technology in Boulder, CO&#160;for their assistance.

The GaN NWs used in these experiments were grown by catalyst-free molecular beam epitaxy (MBE) on Si(111) substrates9. The general procedure for preparing the NW suspension from the substrate with the as-grown NWs is illustrated in Figure 1.
1. Nanowire Suspension Preparation
<ol>
	<li>Cleave a small (&#60;5 mm x&#160;5 mm) piece of the as-grown NWs on the substrate.</li>
	<li>Fill a small capped vial with about 1 ml of isopropanol (IPA).</li>
	<li>Place the cleaved piece into the vial, close the cap and sonicate for about 30 sec in order to remove the NWs from the substrate. Once prepared, the NW suspension remains viable for an extended period of time.</li>
</ol>
2. Substrate Preparation
The substrates used are heavily-doped (&#961; ~0.001-0.005 &#937;-cm) 3-inch Si wafers with 200 nm of thermally-grown SiO2 on both sides.
<ol>
	<li>If electrical contact to the silicon substrate is desired, etch off the oxide from the backside of the wafer using an RIE etcher with the following conditions, O2 flow = 20 sccm, CHF3 flow = 50 sccm, -240 V bias, 120 W for 20 min. This step also helps avoid charging of the specimen during electron microscopy.</li>
	<li>After oxide etch, clean wafer by submersing it face down using a tripod holder into a 1,000 ml beaker with ~100 ml of acetone for 5 min.</li>
	<li>Remove wafer from acetone and immediately rinse off both sides of the wafer using a squirt bottle of IPA over an empty 1,000 ml beaker, which will be used for solvent waste.</li>
	<li>Repeat step 2 using IPA.</li>
	<li>Repeat step 3 rinsing the wafer with deionized H2O over the solvent waste beaker.</li>
	<li>Repeat step 2 using deionized H2O.</li>
	<li>Blow wafer dry using compressed dry N2.</li>
</ol>
3. Nanowire Dispersal
<ol>
	<li>Cleave the clean wafer into 4 equal quarters. Each quarter will have 3 contact patterns deposited on it in the general areas shown in Figures 2A and B.</li>
	<li>Sonicate the vial of NW suspension prior to dispensing in order to get a uniform NW concentration in the suspension.</li>
	<li>Set the micropipette to the desired drop size (3-30 &#956;l) and draw the NW suspension from the vial.</li>
	<li>Take substrate piece (&#188; wafer) that will be used for dispersal and ensure that it is level so that the NW suspension does not migrate away to the edges.</li>
	<li>Dispense the NW suspension onto the (oxidized) front surface of the Si substrate in the general area where the contact pattern will be deposited. If desired, deposit additional drops of the NW suspension in the same area, after the solvent from the previous drop has completely evaporated.</li>
	<li>Repeat step 3.4 for the other 2 areas where a contact pattern will be. Do not dispense the NW suspension from more than 1 growth run on a single substrate piece (&#188; wafer) in order to avoid cross contamination. The dispersal of the NW suspension onto the substrate is illustrated in Figures 2C and D.</li>
	<li>After the final drop of NW suspension has evaporated, place the sample face down in a tripod holder and gently dip in successive baths of acetone and isopropanol to remove unwanted impurities. Rinse in deionized H2O, and blow dry in N2. Do not use squirt bottles or sonicate the solvent during this cleaning process to avoid excess removal of NWs from the surface.</li>
</ol>
4. Photolithography of Contact Pattern
Use standard photolithographic techniques to create the contact pattern in a clean room with ambient conditions of ~20 &#176;C and ~40% relative humidity. Mask aligner intensity (step&#160;4.6), exposure time (step 4.8) and develop time (step 4.9) will be equipment-dependent and should be adjusted to produce maximum pattern definition with a lift-off-resist (LOR) undercut of about 0.5 &#956;m.
<ol>
	<li>Spin lift-off resist onto sample using a two step recipe of (1) 300 rpm for 10 sec (2) 2,000 rpm for 45 sec.</li>
	<li>Place sample on a hot plate to bake for 5 min at 150-170 &#176;C.</li>
	<li>Remove sample and allow to cool for 30 sec and then spin on photoresist using a two step recipe of (1) 1,000 rpm for 3 sec (2) at 5,000 rpm for 45 sec.</li>
	<li>Place sample on a hot plate to bake for 1 min at 115 &#176;C.</li>
	<li>Allow sample to cool for 1 min.</li>
	<li>Calibrate mask aligner to a light intensity of ~1.90 mW/cm2.</li>
	<li>Load sample into mask aligner, with the proper mask for the contact pattern installed.</li>
	<li>Bring sample into contact with mask and expose the sample for 24 sec.</li>
	<li>Develop photoresist by swirling sample in a beaker of developer for 21 sec.</li>
	<li>Rinse with deionized H2O and blow dry with N2.</li>
</ol>
5. Sample Pretreatment Prior to Metal Deposition
Prior to loading the samples into the electron-beam evaporator for metal deposition, give the patterned wafer a UV ozone treatment and a HCl:H2O bath.
<ol>
	<li>Load samples into UV Ozone generator for 10 min with an ultra-high-purity O2 flow rate of 80 sccm.</li>
	<li>After UV ozone treatment, place samples in a HCl:H2O (1:10) solution for 1 min at room temperature.</li>
	<li>Rinse samples with deionized H2O and blow dry gently with N2.</li>
</ol>
6. Electron-beam Evaporation of Contact Metals
<ol>
	<li>Immediately after pretreatment, mount the samples to the platen using screws and clips and secure platen in the e-beam evaporator. Make sure that sufficient Ni and Au are available for deposition.</li>
	<li>Pump down chamber until the pressure is below 1.3 x 10-3 Pa (1 &#956;Torr) (may require to pump overnight).</li>
	<li>Set high voltage to 10 kV and begin rotation of samples at 5 rpm. Make sure shutter is closed.</li>
	<li>Select the Ni crucible and enter parameters for Ni into the crystal rate monitor. Deposit 50 nm (500 &#8491;) of Ni at a deposition rate of ~0.1 nm/s.</li>
	<li>Once Ni source has sufficiently cooled down (~15 min), switch to Au crucible, change the parameters to those for Au, and deposit 100 nm (1,000 &#8491;) of Au at a deposition rate of ~0.1 nm/sec.</li>
	<li>Once Au crucible has cooled down (~10 min), vent chamber and unload sample platen. If unsure of metal thickness, use a profilometer to determine the Ni/Au thickness.</li>
</ol>
7. Contact Metal Lift-off
<ol>
	<li>Remove samples from platen and place in a photoresist stripper bath at room temperature for a few hours to lift off the metal deposited on the photoresist. If desired, elevate the bath temperature to around 50-60 &#176;C to accelerate lift-off.</li>
	<li>If the metal does not come off completely, use a squirt bottle of Remover PG to forcefully remove the remaining undesired metal from the surface. Do not sonicate the sample because this can cause the nanowires to break free from the metal.</li>
	<li>Rinse off the Remover PG from sample with IPA into a solvent waste beaker and place sample into a beaker of clean IPA.</li>
	<li>Repeat step 7.3 using deionized H2O and then blow the sample dry using N2.</li>
</ol>
8. Contact Anneal
Test devices before the contact anneal in order to compare these with annealed devices. Perform the contact anneal of the Ni/Au films using a rapid thermal annealer (RTA) with ultra-high-purity N2/O2 (3:1) as the process gas.
<ol>
	<li>Wait at least 24 hr after removal of contact metal before annealing samples, to ensure the metal contacts have reached equilibrium after deposition.</li>
	<li>Purge the RTA by running the N2/O2 at a temperature of 650 &#176;C for 5 min without any samples.</li>
	<li>Load samples and adjust flow rate of N2/O2 to 1.4 SLPM.</li>
	<li>Anneal samples at 550 &#176;C for 10 min. The temperature ramp rate was ~500 &#176;C/min.</li>
</ol>
9. Ni/Au Film Removal
Since removal of the Ni/Au film is a destructive process, devices are typically imaged and tested before this step. The procedure for the Ni/Au film removal is illustrated in Figure 3.
<ol>
	<li>Wait at least 24 hr after contact anneal before removing the Ni/Au film.</li>
	<li>Cleave a piece of the sample from the area of interest. Make sure size of sample is large enough in order to grab the edges with tweezers without touching the area of interest.</li>
	<li>Secure a SEM pin stub mount in a holder such that the mount can be easily moved or taken out.</li>
	<li>Place a piece of conductive carbon tape flat onto the mount surface. The piece of carbon tape should be larger than the area of the film that is to be removed. A conductive carbon tab that is the precise size of the mount surface works very well for this application. Apply the carbon tape or tab to the mount surface slowly and carefully to ensure that the surface is as smooth as possible.</li>
	<li>Before removing the backing of the tape, using a finger, press hard on the tape so that it is firmly adhering to the mount surface. This is very important so that the tape does not come off with the sample.</li>
	<li>Take a cleaved sample piece and gently lay the area of interest directly onto the carbon tape along the edge of the mount such that the area of the sample that was used for handling with tweezers is hanging off the edge (Figure 3A). Once sample has been placed onto tape, do not remove it for repositioning in order to avoid destroying the Ni/Au film.</li>
	<li>Press firmly down onto the back of the sample using forceps (Figure 3B). Take care not to press too hard on the sample around the mount edges because this can cause the sample to break.</li>
	<li>To remove the substrate, take a clean razor blade or scalpel and gently nudge it in between the substrate and the tape along the edges of the sample (Figure 3C). Carefully repeat this process, nudging the razor blade a little further each time until the substrate can easily be peeled off by grabbing it with tweezers. Using too much force can break the sample. To keep the tape from coming off with substrate, place a pair of forceps or a probe onto the area of the tape that is adjacent to the substrate when prying the substrate off (Figure 3C). The annealed Ni/Au film should remain adhered to the tape (Figure 3D). On average, this step will take about 1 min to complete.</li>
	<li>Image the newly removed Ni/Au film using SEM as soon as possible so as to observe the newly exposed interface of the film before it becomes contaminated.</li>
</ol>

<ol>
	<li>Lu, W., Lieber, C. M. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Semiconductor+nanowires.">Semiconductor nanowires.</a> J. Phys. D: Appl. Phys. 39, R387-R406 (2006).</li><li>Mater Res, A. n. n. u. R. e. v. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=.">.</a> 34, 83-122 (2004).</li><li>Pettersen, S. V., Grande, A. P., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Formation+and+electronic+properties+of+oxygen+annealed+Au/Ni+and+Pt/Ni+contacts+to+p-type.">Formation and electronic properties of oxygen annealed Au/Ni and Pt/Ni contacts to p-type.</a> 22, 186-193 (2007).</li><li>Chen, L. C., Ho, J. K., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=The+Effect+of+Heat+Treatment+on+Ni/Au+Ohmic+Contacts+to+p-Type.">The Effect of Heat Treatment on Ni/Au Ohmic Contacts to p-Type.</a> 176, 773-777 (1999).</li><li>Liday, J., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Investigation+of+NiOx-based+contacts+on+p-GaN.">Investigation of NiOx-based contacts on p-GaN.</a> J. Mater. Sci. Mater. Electron. 19, 855-862 (2008).</li><li>Narayan, J., Wang, H., Oh, T. H., Choi, H. K., Fan, J. C. C. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Formation+of+epitaxial+Au/Ni/Au+ohmic+contacts+to+p-GaN.">Formation of epitaxial Au/Ni/Au ohmic contacts to p-GaN.</a> Appl. Phys. Lett. 81 (21), 3978-3980 (2002).</li><li>Ho, J. K., Jong, C. S., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Low-resistance+ohmic+contacts+to+p-type+GaN+achieved+by+the+oxidation+of+Ni/Au+films.">Low-resistance ohmic contacts to p-type GaN achieved by the oxidation of Ni/Au films.</a> J. Appl. Phys. Lett. 86 (8), 4491-4497 (1999).</li><li>Herrero, A. M., Blanchard, P., et al. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Microstructure+evolution+and+development+of+annealed+Ni/Au+contacts+to+GaN+nanowires.">Microstructure evolution and development of annealed Ni/Au contacts to GaN nanowires.</a> Nanotechnology. 23 (36), 5203.1-5203.10 (2012).</li><li>Bertness, K. A., Roshko, A., Sanford, N. A., Barker, J. M., Davydov, A. V. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Spontaneously+grown+GaN+and+AlGaN+nanowires.">Spontaneously grown GaN and AlGaN nanowires.</a> J. Crystal Growth. 287, 522-527 (2006).</li><li>Herrero, A. M., Bertness, K. A. <a target="_blank" href="http://www.ncbi.nlm.nih.gov/entrez/query.fcgi?db=PubMed&cmd=Search&doptcmdl=Citation&defaultField=Title+Word&term=Optimization+of+Dispersion+and+Surface+Pretreatment+for+Single+GaN+Nanowire+Devices.">Optimization of Dispersion and Surface Pretreatment for Single GaN Nanowire Devices.</a> J. Vac. Sci. Tech. B. 30 (6), 2201.1-2201.5 (2012).</li></ol>

No conflicts of interest declared.

The technique presented allows for analysis of the contact/substrate and contact/NW microstructure of single NW devices. The main advantages of this technique are its low cost and simplicity. It allows for qualitative and quantitative analysis of the contact interface on a large scale with the substrate as well as on a submicrometer scale with individual NWs. The use of carbon tape for the film removal and SEM pin stubs for sample mounting make it possible for analysis using characterization techniques that require clean low-pressure environments. In addition to using SEM for imaging the interface morphology, numerous other characterization techniques can be used, including EDS, x-ray photoelectron spectroscopy (XPS), auger electron spectroscopy (AES) and atomic force microscopy (AFM).
One possible modification to the NW dispersal procedure would be to etch a pattern into the substrate prior to dispersal that shows the specific location of where each contact pattern will be in order for more exact placement of the NW suspension. This will require extra processing steps that increase the complexity of the process as well as the chance for residual contamination. Another issue for the NW dispersal process is the amount of NW suspension that is to be dispersed. The specific amount is dependent on the size of the contact pattern. For the 1 cm2 sized contact pattern that was used in our experiments, a 30 &#956;l sized drop was sufficient to cover the contact pattern area. It is recommended that not more than two applications of NW suspension be applied in a given area in order to avoid excess build-up from the solvent. If a more dense NW population is desired on the substrate, a smaller amount of solvent should be added to the NW suspension during preparation.
The parameters of the photolithography process are dependent on the specific photoresists and developer used, and therefore the contact pattern photolithography may require modification in order to achieve optimal pattern definition. The exact exposure and developing conditions will also vary as a function of the ambient conditions in the clean room. For application of the photoresist, it is recommended that the sample size not be smaller than a quarter wafer and that the contact patterns not be placed along the edge of the sample due to the edge effects on the photoresist. The contact pattern used in these experiments was for producing 2-terminal NW devices, an example of which is shown in Figure 7A. The contact pattern (1 cm2) consisted of 4 arrays of 48 sets of 2 pads (250 &#956;m&#160;x 500 &#956;m) separated by a specific gap size, as shown in Figures 7B and C. Each array has a different gap size; array I is 3 &#956;m, II is 4 &#956;m, III is 5 &#956;m, and IV is 6 &#956;m. As shown in the Representative Results, Ni/Au film removal can also be accomplished without photoresist patterning of the Ni/Au film.
The simplicity of the Ni/Au film removal process makes it fairly straightforward but some steps may take some practice. In particular, steps 7 and 8 should be rehearsed using dummy samples in order to determine the correct amount of force to apply for the film to adhere to the tape without breaking the sample. In order to determine the void area using imaging software, the SEM images of the removed films must be of large uniform areas that are not excessively broken up like that shown in Figure 4C.

Single-NW devices are made by dispersing a NW suspension onto an insulating substrate and forming contact pads on the substrate via conventional photolithography and metal deposition, which results in randomly formed two-terminal devices. A thick SiO2 film on a Si wafer is typically used as an insulating substrate1,2. For metals deposited on a SiO2 surface, a common problem resulting from heat treatment is the occurrence of void formation at the metal/SiO2 interface. In addition to cracking and delamination of the metal film, this void formation can negatively affect device performance from an increase in resistance caused by a reduction of the contact area. Ni/Au contacts oxidized in N2/O2 atmospheres are the predominant contact scheme applied to p-GaN3-7. During heat treatment in a N2/O2, the Ni diffuses to the surface to form NiO and the Au diffuses down to the substrate surface.
In this work, excessive void formation at the contact/NW and contact/SiO2 interfaces was shown to occur during annealing of Ni/Au contacts to NWs on SiO28. The surface morphology of the annealed Ni/Au film, however, does not indicate the existence of voids or the degree to which void formation has occurred. To address this problem, we developed a technique for the removal of Ni/Au contacts and GaN NWs from SiO2/Si substrates in order to analyze the interface of the contact with the substrate and NWs. This technique can be used for the removal of any contact structure that has poor adhesion to the substrate. The Ni/Au films with GaN NWs embedded in them are removed from the SiO2 substrate with carbon tape. The carbon tape is adhered to a standard pin mount for characterization by use of scanning electron microscopy (SEM) along with several other tools. The detailed procedure for the fabrication of single GaN NW devices and analysis of their contact interface morphology are described.

<table><tbody><tr><td colspan="4">&lt;strong&gt;REAGENTS and MATERIALS&lt;/strong&gt;</td></tr><tr><td>Lift-off resist</td><td>MicroChem</td><td>LOR 5A</td><td>Varies according to application</td></tr><tr><td>Photoresist</td><td>Shipley</td><td>1813</td><td>Varies according to application</td></tr><tr><td>Developer</td><td>Rohm and Haas Electronic Materials</td><td>MF CD-26</td><td>Varies according to application</td></tr><tr><td>Photoresist stripper</td><td>MicroChem</td><td>Nano Remover PG</td><td>Varies according to application</td></tr><tr><td>Ni source</td><td>International Advanced Materials</td><td>99.999% purity</td><td></td></tr><tr><td>Au source</td><td>International Advanced Materials</td><td>99.999% purity</td><td></td></tr><tr><td>SiO&lt;sub&gt;2&lt;/sub&gt;/Si wafers</td><td>Silicon Valley Microelectronics</td><td>3-inch &amp;lt;100&gt; N/As 0.001-0.005 ohm-cm, 200 nm thermal oxide</td><td></td></tr><tr><td>Carbon tape</td><td>SPI Supplies</td><td>5072, 8 mm wide</td><td></td></tr><tr><td colspan="4">Solvents are standard semiconductor or research grade. Vendor is not important for the experimental outcome.</td></tr><tr><td colspan="4">Reactive ion etch gases and thermal annealing gases are high purity grade. Vendor is not important for the experimental outcome.</td></tr><tr><td colspan="4">&lt;strong&gt;EQUIPMENT&lt;/strong&gt;</td></tr><tr><td>Ultrasonic cleaner</td><td>Cole-Palmer</td><td>EW-08849-00</td><td>Low power</td></tr><tr><td>Micropipette</td><td>Rainin</td><td>PR-200</td><td>Metered, disposal tips</td></tr><tr><td>Reactive ion etcher</td><td>SemiGroup</td><td>RIE 1000 TP</td><td>Other vendors also used with different process parameters</td></tr><tr><td>Mask aligner</td><td>Karl Suss</td><td>MJB3</td><td>Other vendors also used with different process parameters</td></tr><tr><td>UV ozone cleaner</td><td>Jelight</td><td>Model 42</td><td>Other vendors also used with different process parameters</td></tr><tr><td>E-beam evaporator</td><td>CVC</td><td>SC-6000</td><td>Other vendors also used with different process parameters</td></tr><tr><td colspan="4">* Manufacturers and product names are given solely for completeness. These specific citations neither constitute an endorsement of the product by NIST nor imply that similar products from other companies would be less suitable.</td></tr></tbody></table>

analysis of contact interfaces for single gan nanowire devices

Single GaN nanowire (NW) devices fabricated on SiO2 can exhibit a strong degradation after annealing due to the occurrence of void formation at the contact/SiO2 interface. This void formation can cause cracking and delamination of the metal film, which can increase the resistance or lead to a complete failure of the NW device. In order to address issues associated with void formation, a technique was developed that removes Ni/Au contact metal films from the substrates to allow for the examination and characterization of the contact/substrate and contact/NW interfaces of single GaN NW devices. This procedure determines the degree of adhesion of the contact films to the substrate and NWs and allows for the characterization of the morphology and composition of the contact interface with the substrate and nanowires. This technique is also useful for assessing the amount of residual contamination that remains from the NW suspension and from photolithographic processes on the NW-SiO2 surface prior to metal deposition. The detailed steps of this procedure are presented for the removal of annealed Ni/Au contacts to Mg-doped GaN NWs on a SiO2 substrate.

An example of SEM analysis on annealed Ni/Au films removed from the SiO2 substrate using carbon tape is shown in Figure 4. The surface of a Ni/Au contact prior to removal is shown in Figure 4A. The underside of the same area of that particular Ni/Au film after removal is shown in Figure 4B. Comparison of the surface and underside morphology can help determine if there is a relationship between the two. For example, when the two images are compared, it can be seen that the dark spots in (a) coincide with the dark features in (b). At higher magnifications, critical features of the Ni/Au underside morphology can be discerned. Along with the use of energy dispersive spectroscopy (EDS), in order to determine the composition of the different features of the underside morphology, the general structure of the Ni/Au film on SiO2 after annealing can be ascertained. A removed Ni/Au film that was properly prepared is shown at a lower magnification in Figure 4C. The void formation is uniform across the film and no cracking or breaking of the film has occurred. Figure 4D is an example of a removed Ni/Au film that was poorly prepared. This sample had received no cleaning pretreatment prior to the metal deposition, and the residual contamination produced nonuniform void distribution and large macrovoids that resemble blisters. Upon removal of the film, the tape had come off some from the mount and wrinkled, causing the film to break apart.
One important application of this technique is analyzing the contact/NW interface morphology. Figure 5 shows SEM images of the underside of annealed Ni/Au films that had been deposited onto NWs dispersed onto SiO2/Si substrates. The NWs, which are embedded in the Ni/Au films, also come off with films upon removal with the carbon tape. At larger magnifications, like the image shown in Figure 5A, the distribution of voids relative to the NWs can be observed. At higher magnifications, such as the images in Figures 5B and C, the contact/NW microstructure can be more thoroughly studied. It is not uncommon for NWs to become dislodged from the Ni/Au film upon peeling it off of the substrate, as shown in Figures 5A and C. This allows for the examination of the contact/NW interface that would otherwise be obscured if the NW had remained in place.
A more quantitative analysis can be performed through the use of imaging software. The example shown in Figure 6 is based on the correlation of residual contamination from processing with void formation at the interface of the Ni/Au with the SiO210. The presence of this residual contamination can cause a significant increase in the number of voids observed at the contact/substrate interface. By quantifying the degree of void formation at the contact/substrate interface, the effectiveness of different cleaning methods can be evaluated. These experiments focused on the effectiveness of the various cleaning methods prior to deposition of the Ni/Au onto the SiO2 for the removal of the residual contamination. The area of the voided regions was determined using imaging software. Using SEM images, multiple 100 &#956;m2 areas were analyzed for each sample and the average void area (as a percentage of the total area) for each of the different preparation and cleaning methods was determined. The data is plotted in Figure 6G with the standard deviation of the data set represented by error bars.
<img alt="Figure 1" fo:content-width="5in" src="/files/ftp_upload/50738/50738fig1.jpg" /> 
Figure 1. General procedure for NW suspension preparation and dispersal. <a href="https://www-jove-com.remotexs.ntu.edu.sg/files/ftp_upload/50738/50738fig1highres.jpg" target="_blank">Click here to view larger image</a>.
<img alt="Figure 2" fo:content-width="5in" src="/files/ftp_upload/50738/50738fig2.jpg" /> 
Figure 2. Procedure for dispersal of NW suspension. <a href="https://www-jove-com.remotexs.ntu.edu.sg/files/ftp_upload/50738/50738fig2highres.jpg" target="_blank">Click here to view larger image</a>.
<img alt="Figure 3" fo:content-width="6in" src="/files/ftp_upload/50738/50738fig3.jpg" /> 
Figure 3. Procedure for removal of annealed Ni/Au film from SiO2/Si substrate. (a) Step 9.6, Sample is gently laid onto the mount with carbon tape. (b) Step 9.7, Force is applied to the back of sample. (c) Step 9.8, Removal of substrate from carbon tape using a razor blade. (d) Step 9.8, Annealed Ni/Au film remains adhered to the tape. <a href="https://www-jove-com.remotexs.ntu.edu.sg/files/ftp_upload/50738/50738fig3highres.jpg" target="_blank">Click here to view larger image</a>.
<img alt="Figure 4" fo:content-width="4in" src="/files/ftp_upload/50738/50738fig4.jpg" /> 
Figure 4. (a) SEM image of annealed Ni/Au contact. (b) SEM image of same Ni/Au film shown in (a) after being removed with carbon tape to reveal its underside. (c) Removed Ni/Au film that was properly prepared. (d) Removed Ni/Au film that was poorly prepared. (Images (a) and (b) taken from reference8).&#160;<a href="https://www-jove-com.remotexs.ntu.edu.sg/files/ftp_upload/50738/50738fig4highres.jpg" target="_blank">Click here to view larger image</a>.
<img alt="Figure 5" fo:content-width="4in" src="/files/ftp_upload/50738/50738fig5.jpg" /> 
Figure 5. SEM images of the underside of annealed Ni/Au films that were deposited onto NWs that had been dispersed onto SiO2/Si substrates and then removed with carbon tape. (a) Area showing a NW within the annealed Ni/Au film alongside where a NW had been before dislodging. (b) Close-up view of a NW within the annealed Ni/Au film. (c) Close-up of where a NW had been before dislodging. (Images (b) and (c) taken from reference8).&#160;<a href="https://www-jove-com.remotexs.ntu.edu.sg/files/ftp_upload/50738/50738fig5highres.jpg" target="_blank">Click here to view larger image</a>.
<img alt="Figure 6" fo:content-width="4in" src="/files/ftp_upload/50738/50738fig6.jpg" /> 
Figure 6. SEM images of the underside of annealed Ni/Au films deposited on SiO2 surfaces that had received varying surface treatments. (a)-(c) Samples where the SiO2 surface received no photolithographic processing prior to predeposition cleaning. (d)-(f) Samples where the SiO2 surface received photolithographic processing prior to predeposition cleaning. (g) Values of the areas of the voided regions plotted for each sample shown in (a)-(f). (Images and plot taken from reference10).&#160;<a href="https://www-jove-com.remotexs.ntu.edu.sg/files/ftp_upload/50738/50738fig6highres.jpg" target="_blank">Click here to view larger image</a>.
<img alt="Figure 7" fo:content-width="5.5in" src="/files/ftp_upload/50738/50738fig7.jpg" /> 
Figure 7. (a) SEM image of an individual NW device. (b) Complete contact pattern. (c) Close-up view of contact pattern. <a href="https://www-jove-com.remotexs.ntu.edu.sg/files/ftp_upload/50738/50738fig7highres.jpg" target="_blank">Click here to view larger image</a>.

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Analysis of Contact Interfaces for Single GaN Nanowire Devices

A technique was developed that removes Ni/Au contact metal films from their substrate to allow for the examination and characterization of the contact/substrate and contact/NW interfaces of single GaN nanowire devices.

Single GaN nanowire (NW) devices fabricated on SiO2 can exhibit  a strong degradation after annealing due to the  occurrence of void formation at the ...

analysis-of-contact-interfaces-for-single-gan-nanowire-devices

Nanyang Technological University

Research

JoVE Journal

Engineering

9.4K Views.  National Institute of Standards and Technology. A technique was developed that removes Ni/Au contact metal films from their substrate to allow for the examination and characterization of the contact/substrate and contact/NW interfaces of single GaN nanowire devices.

Video: Analysis of Contact Interfaces for Single GaN Nanowire Devices

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

A quantum computer is a computer composed of quantum bits (qubits) that takes advantage of quantum effects, such as superposition of states and entanglement, to solve certain problems exponentially faster than with the best known algorithms on a classical computer. Gate-defined lateral quantum dots on GaAs/AlGaAs are one of many avenues explored for the implementation of a qubit. When properly fabricated, such a device is able to trap a small number of electrons in a certain region of space. The spin states of these electrons can then be used to implement the logical 0 and 1 of the quantum bit. Given the nanometer scale of these quantum dots, cleanroom facilities offering specialized equipment- such as scanning electron microscopes and e-beam evaporators- are required for their fabrication. Great care must be taken throughout the fabrication process to maintain cleanliness of the sample surface and to avoid damaging the fragile gates of the structure. This paper presents the detailed fabrication protocol of gate-defined lateral quantum dots from the wafer to a working device. Characterization methods and representative results are also briefly discussed. Although this paper concentrates on double quantum dots, the fabrication process remains the same for single or triple dots or even arrays of quantum dots. Moreover, the protocol can be adapted to fabricate lateral quantum dots on other substrates, such as Si/SiGe.

This paper presents a detailed fabrication protocol for gate-defined semiconductor lateral quantum dots on gallium arsenide heterostructures. These nanoscale devices are used to trap few electrons for use as quantum bits in quantum information processing or for other mesoscopic experiments such as coherent conductance measurements.

A quantum computer is a computer composed of quantum bits (qubits) that takes advantage of quantum effects, such as superposition of states and ...

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

In recent years &pi;-conjugated organic semiconductors have emerged as the active material in a number of diverse applications including large-area, low-cost displays, photovoltaics, printable and flexible electronics and organic spin valves. Organics allow (a) low-cost, low-temperature processing and (b) molecular-level design of electronic, optical and spin transport characteristics. Such features are not readily available for mainstream inorganic semiconductors, which have enabled organics to carve a niche in the silicon-dominated electronics market. The first generation of organic-based devices has focused on thin film geometries, grown by physical vapor deposition or solution processing. However, it has been realized that organic nanostructures can be used to enhance performance of above-mentioned applications and significant effort has been invested in exploring methods for organic nanostructure fabrication.	
A particularly interesting class of organic nanostructures is the one in which vertically oriented organic nanowires, nanorods or nanotubes are organized in a well-regimented, high-density array. Such structures are highly versatile and are ideal morphological architectures for various applications such as chemical sensors, split-dipole nanoantennas, photovoltaic devices with radially heterostructured "core-shell" nanowires, and memory devices with a cross-point geometry. Such architecture is generally realized by a template-directed approach. In the past this method has been used to grow metal and inorganic semiconductor nanowire arrays. More recently &pi;-conjugated polymer nanowires have been grown within nanoporous templates. However, these approaches have had limited success in growing nanowires of technologically important &pi;-conjugated small molecular weight organics, such as tris-8-hydroxyquinoline aluminum (Alq3), rubrene and methanofullerenes, which are commonly used in diverse areas including organic displays, photovoltaics, thin film transistors and spintronics.	
Recently we have been able to address the above-mentioned issue by employing a novel "centrifugation-assisted" approach. This method therefore broadens the spectrum of organic materials that can be patterned in a vertically ordered nanowire array. Due to the technological importance of Alq3, rubrene and methanofullerenes, our method can be used to explore how the nanostructuring of these materials affects the performance of aforementioned organic devices. The purpose of this article is to describe the technical details of the above-mentioned protocol, demonstrate how this process can be extended to grow small-molecular organic nanowires on arbitrary substrates and finally, to discuss the critical steps, limitations, possible modifications, trouble-shooting and future applications.

We report a simple method for fabricating an ultrahigh density array of vertically ordered small-molecular organic nanowires. This method allows for synthesis of complex heterostructured hybrid nanowire geometries, which can be inexpensively grown on arbitrary substrates. These structures have potential applications in organic electronics, optoelectronics, chemical sensing, photovoltaics and spintronics.

In  recent years &pi;-conjugated  organic semiconductors have emerged as the active material in a number of  diverse applications including large-area, ...

Monolayer Contact Doping of Silicon Surfaces and Nanowires Using Organophosphorus Compounds

Monolayer Contact Doping (MLCD) is a simple method for doping of surfaces and nanostructures1. MLCD results in the formation of highly controlled, ultra shallow and sharp doping profiles at the nanometer scale. In MLCD process the dopant source is a monolayer containing dopant atoms.
In this article a detailed procedure for surface doping of silicon substrate as well as silicon nanowires is demonstrated. Phosphorus dopant source was formed using tetraethyl methylenediphosphonate monolayer on a silicon substrate. This monolayer containing substrate was brought to contact with a pristine intrinsic silicon target substrate and annealed while in contact. Sheet resistance of the target substrate was measured using 4 point probe. Intrinsic silicon nanowires were synthesized by chemical vapor deposition (CVD) process using a vapor-liquid-solid (VLS) mechanism; gold nanoparticles were used as catalyst for nanowire growth. The nanowires were suspended in ethanol by mild sonication. This suspension was used to dropcast the nanowires on silicon substrate with a silicon nitride dielectric top layer. These nanowires were doped with phosphorus in similar manner as used for the intrinsic silicon wafer. Standard photolithography process was used to fabricate metal electrodes for the formation of nanowire based field effect transistor (NW-FET). The electrical properties of a representative nanowire device were measured by a semiconductor device analyzer and a probe station.

A detailed procedure for surface doping of Silicon interfaces is provided. The ultra-shallow surface doping is demonstrated by using phosphorus containing monolayers and rapid annealing process. The method can be used for doping of macroscopic area surfaces as well as nanostructures.

Monolayer Contact Doping (MLCD) is a simple method for doping of surfaces and nanostructures1. MLCD results in the formation of highly controlled, ultra ...

Evaluating Plasmonic Transport in Current-carrying Silver Nanowires

Plasmonics is an emerging technology capable of simultaneously transporting a plasmonic signal and an electronic signal on the same information support1,2,3. In this context, metal nanowires are especially desirable for realizing dense routing networks4. A prerequisite to operate such shared nanowire-based platform relies on our ability to electrically contact individual metal nanowires and efficiently excite surface plasmon polaritons5 in this information support. In this article, we describe a protocol to bring electrical terminals to chemically-synthesized silver nanowires6 randomly distributed on a glass substrate7. The positions of the nanowire ends with respect to predefined landmarks are precisely located using standard optical transmission microscopy before encapsulation in an electron-sensitive resist. Trenches representing the electrode layout are subsequently designed by electron-beam lithography. Metal electrodes are then fabricated by thermally evaporating a Cr/Au layer followed by a chemical lift-off. The contacted silver nanowires are finally transferred to a leakage radiation microscope for surface plasmon excitation and characterization8,9. Surface plasmons are launched in the nanowires by focusing a near infrared laser beam on a diffraction-limited spot overlapping one nanowire extremity5,9. For sufficiently large nanowires, the surface plasmon mode leaks into the glass substrate9,10. This leakage radiation is readily detected, imaged, and analyzed in the different conjugate planes in leakage radiation microscopy9,11. The electrical terminals do not affect the plasmon propagation. However, a current-induced morphological deterioration of the nanowire drastically degrades the flow of surface plasmons. The combination of surface plasmon leakage radiation microscopy with a simultaneous analysis of the nanowire electrical transport characteristics reveals the intrinsic limitations of such plasmonic circuitry.

Silver nanowires can simultaneously transport electrons and optical information in the form of surface plasmons. A procedure is described here to realize such a shared circuitry and the limitations at propagating both information carriers are evaluated.

Plasmonics is an emerging technology capable of simultaneously transporting a plasmonic signal and an electronic signal on the same information ...

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures

Layer semiconductors with easily processed two-dimensional (2D) structures exhibit indirect-to-direct bandgap transitions and superior transistor performance, which suggest a new direction for the development of next-generation ultrathin and flexible photonic and electronic devices. Enhanced luminescence quantum efficiency has been widely observed in these atomically thin 2D crystals. However, dimension effects beyond quantum confinement thicknesses or even at the micrometer scale are not expected and have rarely been observed. In this study, molybdenum diselenide (MoSe2) layer crystals with a thickness range of 6-2,700 nm were fabricated as two- or four-terminal devices. Ohmic contact formation was successfully achieved by the focused-ion beam (FIB) deposition method using platinum (Pt) as a contact metal. Layer crystals with various thicknesses were prepared through simple mechanical exfoliation by using dicing tape. Current-voltage curve measurements were performed to determine the conductivity value of the layer nanocrystals. In addition, high-resolution transmission electron microscopy, selected-area electron diffractometry, and energy-dispersive X-ray spectroscopy were used to characterize the interface of the metal&#8211;semiconductor contact of the FIB-fabricated MoSe2 devices. After applying the approaches, the substantial thickness-dependent electrical conductivity in a wide thickness range for the MoSe2-layer semiconductor was observed. The conductivity increased by over two orders of magnitude from 4.6 to 1,500 &#937;&#8722;1 cm&#8722;1, with a decrease in the thickness from 2,700 to 6 nm. In addition, the temperature-dependent conductivity indicated that the thin MoSe2 multilayers exhibited considerably weak semiconducting behavior with activation energies of 3.5-8.5 meV, which are considerably smaller than those (36-38 meV) of the bulk. Probable surface-dominant transport properties and the presence of a high surface electron concentration in MoSe2 are proposed. Similar results can be obtained for other layer semiconductor materials such as MoS2 and WS2.

We describe the approaches for the device fabrication and electrical characterization of molybdenum diselenide (MoSe2) layer semiconductor nanostructures with different thicknesses. In addition, the fabrication of ohmic contacts for MoSe2-layer nanocrystals by the focused-ion beam deposition method using platinum (Pt) as a contact metal is described.

Layer semiconductors with easily processed two-dimensional (2D) structures exhibit indirect-to-direct bandgap transitions and superior transistor ...

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-&#954; dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive ...

Fabrication of Carbon Nanotube High-Frequency Nanoelectronic Biosensor for Sensing in High Ionic Strength Solutions

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them good candidates for high sensitivity biosensors. When a charged molecule binds to such a sensor surface, it alters the carrier density5 in the sensor, resulting in changes in its DC conductance. However, in an ionic solution a charged surface also attracts counter-ions from the solution, forming an electrical double layer (EDL). This EDL effectively screens off the charge, and in physiologically relevant conditions ~100 millimolar (mM), the characteristic charge screening length (Debye length) is less than a nanometer (nm). Thus, in high ionic strength solutions, charge based (DC) detection is fundamentally impeded6-8.
We overcome charge screening effects by detecting molecular dipoles rather than charges at high frequency, by operating carbon nanotube field effect transistors as high frequency mixers9-11. At high frequencies, the AC drive force can no longer overcome the solution drag and the ions in solution do not have sufficient time to form the EDL. Further, frequency mixing technique allows us to operate at frequencies high enough to overcome ionic screening, and yet detect the sensing signals at lower frequencies11-12. Also, the high transconductance of SWNT transistors provides an internal gain for the sensing signal, which obviates the need for external signal amplifier.
Here, we describe the protocol to (a) fabricate SWNT transistors, (b) functionalize biomolecules to the nanotube13, (c) design and stamp a poly-dimethylsiloxane (PDMS) micro-fluidic chamber14 onto the device, and (d) carry out high frequency sensing in different ionic strength solutions11.

We describe the device fabrication and measurement protocol for carbon nanotube based high frequency biosensors. The high frequency sensing technique mitigates the fundamental ionic (Debye) screening effect and allows nanotube biosensor to be operated in high ionic strength solutions where conventional electronic biosensors fail. Our technology provides a unique platform for point-of-care (POC) electronic biosensors operating in physiologically relevant conditions.

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them ...

Bioengineering

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of nanowires. DEP is used for nanowire analysis, characterization, and for solution-based fabrication of semiconducting devices. The method works by applying an alternating electric field between metallic electrodes. The nanowire formulation is then dropped onto the electrodes which are on an inclined surface to create a flow of the formulation using gravity. The nanowires then align along the gradient of the electric field and in the direction of the liquid flow. The frequency of the field can be adjusted to select nanowires with superior conductivity and lower trap density. 
In this work, flow-assisted DEP is used to create nanowire field effect transistors. Flow-assisted DEP has several advantages: it allows selection of nanowire electrical properties; control of nanowire length; placement of nanowires in specific areas; control of orientation of nanowires; and control of nanowire density in the device. 
The technique can be expanded to many other applications such as gas sensors and microwave switches. The technique is efficient, quick, reproducible, and it uses a minimal amount of dilute solution making it ideal for the testing of novel nanomaterials. Wafer scale assembly of nanowire devices can also be achieved using this technique, allowing large numbers of samples for testing and large-area electronic applications.

In this paper, flow assisted dielectrophoresis is demonstrated for the self-assembly of nanowire devices. The fabrication of a silicon nanowire field effect transistor is shown as an example.

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of ...

A Closed-Type Wireless Nanopore Electrode for Analyzing Single Nanoparticles

Measuring the intrinsic features of single nanoparticles by nanoelectrochemistry holds deep fundamental importance and has potential impacts in nanoscience. However, electrochemically analyzing single nanoparticles is challenging, as the sensing nanointerface is uncontrollable. To address this challenge, we describe here the fabrication and characterization of a closed-type wireless nanopore electrode (WNE) that exhibits a highly controllable morphology and outstanding reproducibility. The facile fabrication of WNE enables the preparation of well-defined nanoelectrodes in a general chemistry laboratory without the use of a clean room and expensive equipment. One application of a 30 nm closed-type WNE in analysis of single gold nanoparticles in the mixture is also highlighted, which shows a high current resolution of 0.6 pA and high temporal resolution of 0.01 ms. Accompanied by their excellent morphology and small diameters, more potential applications of closed-type WNEs can be expanded from nanoparticle characterization to single molecule/ion detection and single-cell probing.

Here, we present a protocol for fabrication of a closed-type wireless nanopore electrode and subsequent electrochemical measurement of single nanoparticle collisions.

Measuring the intrinsic features of single nanoparticles by nanoelectrochemistry holds deep fundamental importance and has potential impacts in ...

Chemistry

Preparation of Silicon Nanowire Field-effect Transistor for Chemical and Biosensing Applications

Surveillance using biomarkers is critical for the early detection, rapid intervention, and reduction in the incidence of diseases. In this study, we describe the preparation of polycrystalline silicon nanowire field-effect transistors (pSNWFETs) that serve as biosensing devices for biomarker detection. A protocol for chemical and biomolecular sensing by using pSNWFETs is presented. The pSNWFET device was demonstrated to be a promising transducer for real-time, label-free, and ultra-high-sensitivity biosensing applications. The source/drain channel conductivity of a pSNWFET is sensitive to changes in the environment around its silicon nanowire (SNW) surface. Thus, by immobilizing probes on the SNW surface, the pSNWFET can be used to detect various biotargets ranging from small molecules (dopamine) to macromolecules (DNA and proteins). Immobilizing a bioprobe on the SNW surface, which is a multistep procedure, is vital for determining the specificity of the biosensor. It is essential that every step of the immobilization procedure is correctly performed. We verified surface modifications by directly observing the shift in the electric properties of the pSNWFET following each modification step. Additionally, X-ray photoelectron spectroscopy was used to examine the surface composition following each modification. Finally, we demonstrated DNA sensing on the pSNWFET. This protocol provides step-by-step procedures for verifying bioprobe immobilization and subsequent DNA biosensing application.

We describe key steps for biosensing by using polysilicon nanowire field-effect transistors, including the preparation of the device and the immobilization and confirmation of a DNA molecular probe on the nanowire surface, as well as conditions for DNA sensing.

Surveillance using biomarkers is critical for the early detection, rapid intervention, and reduction in the incidence of diseases. In this study, we ...