Part of the work has been performed in the project JEMSiP_3D, which is funded by the Public Authorities in France, Germany, Hungary, The Netherlands, Norway and Sweden, as well as by the ENIAC Joint Undertaking. The authors would like to thank the Dimes Technology Centre staff for processing support.

注意:使用前请咨询所有相关的材料安全数据表（MSDS）。几个在该制造工艺中使用的化学品是剧毒和致癌性。相比，他们的大部分对手纳米材料可能有额外的危险。用设备，化学品或纳米材料工作时，包括利用工程控制（通风柜）和个人防护装备（防护眼镜，手套，无尘服）的请使用一切适当的安全措施。 1.对准标记定义为光刻<ol><li>开始与单面抛光的工业级硅（100）晶片与n或p型掺杂。 </li><li>外套与正性光刻胶的1.4微米的晶片。在130℃下进行90秒的六甲基二硅氮烷（HMDS）处理，以促进光致抗蚀剂，接着在晶片上的冷板，旋涂以适当的速度（3500转）的冷却的粘接性，和一个90秒的软烘烤一牛逼95℃。 </li><li>使用光刻掩模和曝光工具暴露对准标记，曝光量为120mJ / cm 2以下。 </li><li>执行一个水坑的发展过程。执行90秒115℃曝光后烘烤，接着60秒显影用显影剂和90秒的硬烘烤，在100℃以固化该抗蚀剂。 </li><li>用显微镜检查，如果在抗蚀剂中的开口是正确的尺寸。 </li><li>蚀刻用Si氯等离子体蚀刻的120纳米。该厚度提供了良好的对比度在这项工作中所用的曝光工具的自动对准系统。例如使用感应耦合等离子体（ICP）:40分之20SCCM 的 O 2 / CF 4，5毫乇，五百分之六十〇 W¯¯压板/ ICP RF功率，10秒氧化物突破蚀刻，接着四十零分之八十SCCM Cl 2中/ HBr的，60毫托，五百分之二十〇W¯¯压板/ ICP的射频功率，35秒硅蚀刻。 </li><li>使用氧等离子体汽提塔，除去光致抗蚀剂（1千瓦，400 SCCM O 2与endpoINT探测和2分钟过腐蚀）。作为光致抗蚀剂是由像丙酮等离子体正常溶剂固化，不能使用。 </li><li>清洁晶圆。首先把它们用于在99％HNO 3，接着漂洗在去离子水中10分钟，直到水的电阻率是5兆欧（有机清洁）。在此之后清洗晶片在110℃下在65％HNO 3 10分钟，随后用DI水漂洗直到水的电阻率是5兆欧（金属清洁）。使用冲洗器干燥器来干燥的晶片。 </li></ol> 2.底部金属和层间电介质沉积<ol><li>使用磁控溅射沉积经由测试的底部金属层。一叠三个金属层需要被沉积:500纳米的Ti，TiN的为50nm，和100nm的钛。第一Ti层是降低堆栈的电阻，使TiN是实际的支撑层为碳纳米管的生长，并且顶Ti为防止等离子体损伤使TiN蚀刻SiO 2层12时</suP&gt;。执行使用纯Ti靶，用Ar等离子体，在350℃的基板温度的Ti溅射。对于TiN的反应性溅射的Ar使用和 N 2的组合，再次在350℃衬底温度下进行。 </li><li>使用等离子体增强化学汽相沉积（PECVD），沉积1微米厚的层的 SiO 2。这里原硅酸四乙酯（TEOS）用作前体在350℃的台板温度。 <ol><li>检查SiO 2层的使用适当的工具的厚度，例如是反射或椭圆仪。 </li></ol></li><li>外套晶片与1.4微米阳性光致抗蚀剂的，从一个90秒的HMDS处理在130℃，接着在晶片上的冷板，旋涂以适当的速度（3500转）冷却，并以90秒的软烘烤在95℃下。 </li><li>使用光刻掩模和曝光工具，露出开口的所需图案，这将在后面蚀刻到SiO 2的吨Ó形成通孔，对准到对准标记，曝光量140毫焦/厘米2。 </li><li>执行开始以90秒115℃的后曝光烘烤的单个水坑开发过程，接着60秒显影用显影剂和90秒的硬烘烤，在100℃。 </li><li>用显微镜检查，如果在抗蚀剂中的开口是正确的尺寸和如果叠加到对准标记是正确的。 </li><li>等离子体蚀刻接触开口中的 SiO 2。例如，使用三极管等离子刻蚀机与C 2 F 6 /瑞郎3一百四十四分之三十六SCCM在180毫托和300瓦的射频功率。如果需要的话，进行一个测试晶片上的蚀刻速率试验，以最小化过蚀刻至5％-10％的时间。 注意:虽然在Ti是耐在此氟化学反应蚀刻，长时间暴露于等离子体，将导致在Ti层的物理蚀刻。如果TiN层暴露于等离子体，这将有负面influen铈对碳纳米管12的生长。不使用湿法蚀刻，因为这将导致在开口过多加宽，使得顶部金属部分4有问题的。 </li><li>在0.55％的HF去除牺牲Ti层通过湿法蚀刻进行60秒。蚀刻冲洗用DI水晶片直到水电阻率之后是5兆欧并使用冲洗器干燥器来干燥的晶片。 注意:使用显微镜它能如果在Ti层被蚀刻进行检查，在TiN层将具有金棕色颜色，而Ti为金属灰色。 </li></ol> 3.催化剂沉积和碳纳米管的生长<ol><li>蒸发Co的5纳米使用电子束蒸发器。抽空直到至少2×10 -6乇 ，以及沉积，以除去任何水膜前加热下使用真空灯晶片至60℃。光致抗蚀剂用于限定接触开口被保持在晶片上，以提供在所述的 SiO 2的催化剂，以接触开口的自对准。 </li><li>删除接触开口外联合通过剥离。钴发现四氢呋喃（THF），得到最好的剥离结果和生长在低温下。N-甲基 -2-吡咯烷酮（NMP），这是以前用于铁蒸发后剥离，发现损坏联合太这样的程度，以防止任何对准的碳纳米管的生长。把该晶片15分钟，在超声浴用THF在35℃。冲洗DI水5分钟，干燥用旋转器或氮气枪。 </li><li>检查显微镜下的晶圆检查光刻胶残渣。如果残留物留执行THF更长的超声处理，并选择使用一种特殊的柔软的棉拭子剥离目的而手动擦去残留物。 </li><li>采用低压化学气相沉积（LPCVD）进行碳纳米管的生长。通过加入50sccm的C 2 H 2 8分钟的预退火，在350℃用700标准立方厘米的 H 2在80毫巴，随后碳纳米管的生长:使用以下配方。在350℃，60增长的分给了大约1微米的碳纳米管。如有必要，执行测试的生长来调节高度，这应该是相同的厚度与SiO 2层。冷却反应器，并清除，使用N 2。 </li><li>使用扫描电子显微镜，或通过制备的横截面，以检查CNT的高度的开口内下45°倾斜。 </li><li>检查使用拉曼光谱，以确定在CNT 18的结晶性的样品。 </li></ol> 4.顶边金属化<ol><li>使用磁控溅射沉积顶部金属。如Ti是一个良好的金属用于接触碳纳米管19， ​​第一溅射100nm的钛，接着为2μm的Al（1％的Si）的不破坏真空。 </li><li>外套与3.1微米阳性光致抗蚀剂具有更高的粘度，从一个90秒的HMDS处理在130℃，接着在晶片上的冷板，旋涂以3000rpm的冷却，并以90秒的软烘烤在晶片95C。 </li><li>使用光刻掩模和曝光工具暴露对准到对准标记的顶部金属图案，曝光量420毫焦/厘米2，-1焦点。 </li><li>执行一个水坑的发展过程。这开始于一个90秒115℃曝光后烘烤，接着使用显影剂和90秒的硬烘烤，在100℃下60秒显影。 </li><li>用显微镜检查，如果在抗蚀剂的线是正确的尺寸和如果叠加到标记是正确的。 </li><li>蚀刻使用氯离子腐蚀的钛/铝堆栈。例如使用感应耦合等离子体:40分之30SCCM Cl 2中/ HBr的，5毫乇，五百分之四十零W¯¯滚筒/ ICP RF功率与终点探测和80％过蚀刻使用15/30 SCCM Cl 2中/ HBr的。 </li><li>使用氧等离子体汽提塔，除去光致抗蚀剂（1千瓦，400 SCCM O 2与端点检测和2分钟过腐蚀）。如果金属覆盖面不完整（ 即每年大约有针孔CNT）使用有机溶剂（如NMP）中，除去光致抗蚀以防止等离子体损坏碳纳米管。 </li><li>清洁晶圆。把它们用于在99％HNO 3，随后用DI水漂洗10分钟，直到水的电阻率是5兆欧（有机清洁）。使用冲洗器干燥器来干燥的晶片。 </li></ol> 5.测量<ol><li>使用根据制造商的说明用扫描电子显微镜来检查晶片的顶部金属化。 注意:如果必要的晶片可以机械地切割，以便通过使用90°的样品倾斜，从而导致在图像进行检查的完整的CNT，如图3由于样品是导电的，必须使用没有额外的处理步骤和该样品可以直接安装到扫描电镜。通常，可以使用的15或20千伏高电压的加速，但是，如果SiO 2层被充电了太多这可以减小吨O 5千伏。 </li><li>执行4点使用与半导体参数分析仪的组合的探针站，如图1和 Vollebregt 等人 16所述探头IV测量。 注意:通常从-0.5到0.5伏的电压扫描就足够了，如通过一个互连的电势降的理想是小的。通过使用4点探针设置探针接触针，并将设置的配线电阻的接触电阻被省略。 </li></ol>

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</ol>

The authors have nothing to disclose.

图1显示制造在这项工作中的结构的示意图，并且其被用于4点探针测量。作为电位通过探针携带没有电流测量，准确的电位降（Vħ-V L），在中央CNT束及其触点的金属可以被测量。更大直径的CNT束被用于接触从接触垫的底TiN层，以减少用于当前迫使探头的总电阻并最大化在中央CNT束中的电势降。 如从图2可以看出，在CNT被成功地生长蚀刻在SiO 2的带长度大致相同的孔（1微米）的深度的开口内。至关重要的是，在CNT的长度是大致相同的孔的深度，以达到顶部金属接触的保形涂层。该包出现非iform，这也有助于该金属的保形涂层。管的平直度和垂直取向可以清楚地看到，在图3中显示的横截面。通过计数，该CNT束的密度估计为周围5×10 10支/ cm 2。使用透射电子显微镜在管的平均直径被发现是8纳米，如别处16被示出。由于低生长温度在CNT壁包含很多缺陷使得确定的壁困难的数目。将管似乎具有一个中空芯，虽然竹道口已观察到。的横截面还示出了底部的TiN层，和牺牲Ti层这部分是在SiO 2下方的湿蚀刻过程中被除去。如果开口被置于闭合在一起牺牲Ti层的蚀刻时间可能要进行优化，以尽量减少钻蚀，以防止氧化物脱层。由于孔的干蚀刻，在在SiO 2和CNT束之间的间距是最小的，这是至关重要的，以防止溅射Ti和Al从围绕该CNT束形成短路。 使用CNT的拉曼数据的结晶（或质量）可以调查。由于不同的拉曼乐队是接近波段的每一个，其他的反褶积是必要的，因为在别处18描述。从图 4中的拉曼数据显而易见的是，一个强大的D和D&#39;带可以观察到，这是由拉曼引起有缺陷的散射，而G带是关系到CC键。另外两个频段都被包括更精确的拟合微弱的拉曼特征。 已知的是，低的生长温度中在一个较低的CNT品质18通用的结果。一般对D超过G辉度比（I D / G）是用来评估石墨材料，这是在图4 1.1的质量。作为具有被EN所示，例如法拉利和罗伯逊20，照顾有只使用这个频段的比例时，必须考虑。与CNT的质量日益提高，首先将I D / G比的增加，直到达到一定量的结晶之后将比率单调减小。由于非常低的生长温度，在CNT在这项工作中出现有低于该阈值16的结晶度。在这些情况下，全宽半值D带的可用于比较制造在不同的工艺条件18的CNT样品。可以预期，该CNT的低质量将显著影响电气性能。 从图 5中的IV特性几乎完全线性行为来看，CNT与顶部和底部金属层之间的接触是欧姆。束的电阻与直径，这是可以预料的是更的CNT可以在的Paral进行减小LEL较大的包。该CNT和金属之间的良好接触被归因于使用的Ti 19，和TiN这是抗氧化21更有弹性。此外，我们发现，由于缺乏任何电介质覆盖物的步骤在CNT的生长后（使用例如旋涂玻璃），一些东西，经常使用在文献中，结合化学机械研磨（CMP）22,23，到碳纳米管的接触电阻低，由于的碳纳米管尖端在顶部金属24埋入。 当比较电阻率的碳纳米管束与文献中，如在图6中进行，其结果是中在文献中的平均值。然而，在这项工作中所用的生长温度是记录低。 Yokoyama等人的结果。 图13是在文献中报道的最低电阻率，仅使用一个40℃的较高的生长温度。然而，用于联合面值设备在工作​​中视察沉积可能无法扩展到大批量生产。显然，电阻率下降而增加的生长温度，其可以是有利的应用允许较高的生长温度。当比较该CNT电阻率捆绑与传统的互连金属一样的Cu（1.7μΩ-cm）的，很明显，需要大幅减少电阻率。改善CNT与束密度的质量，通过优化生长条件下，将需要。这具有不增加的生长温度下进行，以允许用现代的低κ材料和柔性基板集成。 因此，我们已经证明了集成的低温碳纳米管的生长，并集成到标准的半导体制造技术。这种技术已被用于通过测试结构来制造的CNT，并在最近已申请的CNT超级电容器25的制造&lt;/ SUP&gt;。

铜和钨，这是目前用于国家的最先进的非常大规模集成电路（VLSI）技术的互连金属，正在接近的可靠性和电导率1项自己的体能极限。而向下缩放晶体管通常可以提高它们的性能，但实际上增加了电阻和互连的电流密度。这导致互连支配在延迟和功耗2方面的集成电路（IC）的性能。 碳纳米管（CNT）被建议作为替代的Cu和W的金属化，特别是对垂直互连（通孔），为的CNT可以很容易地被生长垂直3。碳纳米管已被证明具有优良的电可靠性，允许高达1000倍更高的电流密度比铜4。此外，CNT不会从表面和晶界散射受到影响，这是增加第r铜esistivity在纳米尺度5。最后，碳纳米管已经被证明是优良的热导体 6，其中所用的热管理在VLSI芯片帮助。 对于碳纳米管在VLSI技术成功的集成是很重要的，对于碳纳米管的生长过程是用半导体制造兼容。这要求使用的材料和这被认为是兼容和可扩展的，以大规模的制造设备的CNT（&lt;400℃）的低温生长。虽然CNT测试过孔许多实例已被证明在文献中7,8,9,10,11,12,13,14，大多数这些使用铁作为催化剂，它被认为是在集成电路中的污染物的制造15。此外，在许多这些作品中使用的生长温度高于400℃的上限要高得多。优选的CNT甚至应种植在350℃以下，为了让拥有现代化的低κ电介质或灵活的集成基材。 在这里，我们提出了一个可扩展的方法生长碳纳米管在温度低至350℃下使用钴作为催化剂 16。该方法是用于制造不同电结构由垂直对准的CNT的集成电路，从互连和电极，以超级电容器和场致发射装置的兴趣。钴催化剂金属通常用在集成电路制造为硅化物的17的制造中，而氮化钛是一种经常用于阻挡材料7。此外，我们证明了制造CNT的测试孔，而只能使用从标准的半导体制造技术的过程。由此，CNT测试过孔被制造，检查通过扫描电子显微镜（SEM）和拉曼光谱，并且电特征。

<table><tbody><tr><td>Si (100) wafer 4&quot;</td><td>International Wafer Service</td><td></td><td>Resisitivity: 2-5 m&amp;Omega;-cm, thickness: 525 &amp;micro;m&amp;nbsp;</td></tr><tr><td>Ti-sputter target (99.995% purity)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Al (1% Si)-sputter target (99.999% purity)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Co (99.95% purity)</td><td>Kurt J. Lesker</td><td></td><td></td></tr><tr><td>SPR3012 positive photoresist</td><td>Dow Electronic Materials</td><td></td><td></td></tr><tr><td>MF-322 developer</td><td>Dow Electronic Materials</td><td></td><td></td></tr><tr><td>HNO&lt;sub&gt;3&lt;/sub&gt; (99.9%)</td><td>KMG Ultra Pure Chemicals</td><td></td><td></td></tr><tr><td>HNO&lt;sub&gt;3&lt;/sub&gt; (69.5%)</td><td>KMG Ultra Pure Chemicals</td><td></td><td></td></tr><tr><td>HF 0.55%</td><td>Honeywell</td><td></td><td></td></tr><tr><td>Tetrahydrofuran</td><td>JT Baker</td><td></td><td></td></tr><tr><td>Acetone</td><td>Sigma-Aldrich</td><td></td><td></td></tr><tr><td>ECI3027 positive photoresist</td><td>AZ</td><td></td><td></td></tr><tr><td>Tetraethyl orthosilicate (TEOS)</td><td>Praxair</td><td></td><td></td></tr><tr><td>N&lt;sub&gt;2&lt;/sub&gt; (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>O&lt;sub&gt;2&lt;/sub&gt; (99.9999%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>CF&lt;sub&gt;4&lt;/sub&gt; (99.9970%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Cl&lt;sub&gt;2&lt;/sub&gt; (99.9900%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>HBr (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>Ar (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>C&lt;sub&gt;2&lt;/sub&gt;F&lt;sub&gt;6&lt;/sub&gt; (99.9990%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>CHF&lt;sub&gt;3&lt;/sub&gt; (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>H&lt;sub&gt;2&lt;/sub&gt; (99.9950%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>C&lt;sub&gt;2&lt;/sub&gt;H&lt;sub&gt;2&lt;/sub&gt; (99.6000%)</td><td>Praxair</td><td></td><td></td></tr><tr><td>EVG 120 coater/developer</td><td>EVG</td><td></td><td></td></tr><tr><td>ASML PAS5500/80 waferstepper</td><td>ASML</td><td></td><td></td></tr><tr><td>SPTS &amp;Omega;mega 201 plasma etcher</td><td>SPTS</td><td></td><td>Used for Si and metal etching</td></tr><tr><td>SPTS &amp;Sigma;igma sputter coater</td><td>SPTS</td><td></td><td></td></tr><tr><td>Novellus Concept One PECVD</td><td>LAM</td><td></td><td></td></tr><tr><td>Drytek 384T plasma etcher</td><td>LAM</td><td></td><td>Used for oxide etching</td></tr><tr><td>CHA Solution e-beam evaporator</td><td>CHA</td><td></td><td></td></tr><tr><td>AIXTRON BlackMagic Pro CVD tool</td><td>AIXTRON</td><td></td><td>Carbon nanotube growth</td></tr><tr><td>Philips XL50 scanning electron microscope</td><td>FEI</td><td></td><td></td></tr><tr><td>Tepla 300</td><td>PVA TePla</td><td></td><td>Resist plasma stripper</td></tr><tr><td>Avenger rinser dryer</td><td>Microporcess Technologies</td><td></td><td></td></tr><tr><td>Leitz MPV-SP reflecometer</td><td>Leitz</td><td></td><td></td></tr><tr><td>Renishaw inVia Raman spectroscope</td><td>Renishaw</td><td></td><td></td></tr><tr><td>Agilent 4156C parameter spectrum analyzer</td><td>Agilent</td><td></td><td></td></tr><tr><td>Cascade Microtech probe station</td><td>Cascade Microtech</td><td></td><td></td></tr></tbody></table>

fabrication of low temperature carbon nanotube vertical interconnects compatible with semiconductor technology

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-&#954; dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

在这项工作中所用的测量结构的设计可以在图1中找到。通过采用这样的结构的碳纳米管束电阻和金属碳纳米管接触电阻的测量可以精确地确定，因为探针和导线电阻被规避。束的电阻为所述CNT束的质量和密度的测量。为了确定不同长度的接触电阻束应测量。 碳纳米管的典型SEM图像，在350℃生长用于从金属化之前的顶部取在45°倾斜60分钟，如图2。这种图像是检查有用的，如果在CNT的生长时间是否正确，以便设置为得到的长度相同的SiO 2层的厚度。制备由机械切割检查由金属化后在相同的晶片的扫描电镜的横截面示于图3中 。这可以bë用于确定CNT的对准，它们的密度（例如是计数CNT的每单位长度的数量），并且如果一个高分辨率的SEM用于确定它们的直径。也将CNT和金属层之间的接触面积可以调查。 共同生长的CNT的拉曼光谱在350℃显示于图4。拉曼光谱是一种强大的技术用于调查该CNT 18的结晶度，并且可以例如被用来优化所述碳纳米管的生长参数以获得最高的质量CNT。四测量使用四点探针进行的结构，并显示在图5中 ，当第四行为是线性的，表示在CNT和金属触点之间的欧姆接触。从斜坡的电阻可被确定。从电阻和电阻率可以计算束的尺寸，这对于这些碳纳米管束相比较文学如图 6所示。 <img alt="图1" src="/files/ftp_upload/53260/53260fig1.jpg" /> 图中的这项工作中使用4点探针测量结构1的设计。在图中，暗黄色层指示的TiN，黑色管该CNT束，和金属层中的Ti和Al栈。是为了清楚起见省略牺牲钛层和氧化是半透明的。探头连接的电气4点探针测量显示。 <a href="https://www-jove-com.remotexs.ntu.edu.sg/files/ftp_upload/53260/53260fig1large.jpg" target="_blank">请点击此处查看该图的放大版本。</a> <img alt="图2" src="/files/ftp_upload/53260/53260fig2.jpg" /> 一个碳纳米管束图2俯视SEM图像。这说明在接触开口成长了2微米宽的碳纳米管束将其内蚀刻在SiO 2。这个数字已经被修改16，经许可爱思唯尔。 <a href="https://www-jove-com.remotexs.ntu.edu.sg/files/ftp_upload/53260/53260fig2large.jpg" target="_blank">请点击此处查看该图的放大版本。</a> <img alt="图3" src="/files/ftp_upload/53260/53260fig3.jpg" /> 图碳纳米管经由3. SEM横截面。一个2微米宽和1微米长的CNT试验通过截面使用机械切割金属化后制备。这个数字已经被修改16，经许可爱思唯尔。 <a href="https://www-jove-com.remotexs.ntu.edu.sg/files/ftp_upload/53260/53260fig3large.jpg" target="_blank">请点击此处查看该图的放大版本。</a> <img alt="图4" src="/files/ftp_upload/53260/53260fig4.jpg" /> 使用Co产生的CNT束生长的图4.拉曼光谱<html>吨350℃。的拉曼频带的名称表示。黑色曲线显示了原始测量数据。对于洛伦兹拟合进行的所有频段（绿色虚线），除非它是拟合高斯18的D&#39;乐队。 <a href="https://www-jove-com.remotexs.ntu.edu.sg/files/ftp_upload/53260/53260fig4large.jpg" target="_blank">请点击此处查看该图的放大版本。</a> <img alt="图5" src="/files/ftp_upload/53260/53260fig5.jpg" /> 图5. IV测量的碳纳米管测试通孔直径不同的符号表示的测量数据，而实线表示拟合到测量数据的线性最小二乘。从线性拟合的斜率所确定的不同通路的电阻抗表示。这个数字已被修改为 16，与爱思唯尔的权限。tp_upload / 53260 / 53260fig5large.jpg"目标="_空白"&gt;点击此处查看该图的放大版本。 <img alt="图6" src="/files/ftp_upload/53260/53260fig6.jpg" /> 图的CNT束的电阻率与文献值6.比较。电阻率从电阻和通过尺寸计算出的。它与从文献值进行比较，和CNT通孔制成在不同温度下使用本工作中描述的方法。这个数字已经被修改16，经许可爱思唯尔。 <a href="https://www-jove-com.remotexs.ntu.edu.sg/files/ftp_upload/53260/53260fig6large.jpg" target="_blank">请点击此处查看该图的放大版本。</a>

Watch this Scientific Journal Video about Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology at JoVE.com

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

低温碳纳米管垂直互连的制作兼容半导体技术

We demonstrate a method for the low temperature growth (350 &#176;C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive ...

fabrication-low-temperature-carbon-nanotube-vertical-interconnects

Nanyang Technological University

Research

JoVE Journal

Engineering

7.7K 次观看.  Delft University of Technology. A method for the growth of low temperature vertically-aligned carbon nanotubes, and the subsequent fabrication of vertical interconnect electrical test structures using semiconductor fabrication is presented.

视频: Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

Fabrication, Densification, and Replica Molding of 3D Carbon Nanotube Microstructures

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip devices, and their applications. In particular, capabilities for cost-effective fabrication of polymer microstructures were transformed by the advent of soft lithography and other micromolding techniques 1, 2, and this led a revolution in applications of microfabrication to biomedical engineering and biology. Nevertheless, it remains challenging to fabricate microstructures with well-defined nanoscale surface textures, and to fabricate arbitrary 3D shapes at the micro-scale. Robustness of master molds and maintenance of shape integrity is especially important to achieve high fidelity replication of complex structures and preserving their nanoscale surface texture. The combination of hierarchical textures, and heterogeneous shapes, is a profound challenge to existing microfabrication methods that largely rely upon top-down etching using fixed mask templates. On the other hand, the bottom-up synthesis of nanostructures such as nanotubes and nanowires can offer new capabilities to microfabrication, in particular by taking advantage of the collective self-organization of nanostructures, and local control of their growth behavior with respect to microfabricated patterns. 
Our goal is to introduce vertically aligned carbon nanotubes (CNTs), which we refer to as CNT "forests", as a new microfabrication material. We present details of a suite of related methods recently developed by our group: fabrication of CNT forest microstructures by thermal CVD from lithographically patterned catalyst thin films; self-directed elastocapillary densification of CNT microstructures; and replica molding of polymer microstructures using CNT composite master molds. In particular, our work shows that self-directed capillary densification ("capillary forming"), which is performed by condensation of a solvent onto the substrate with CNT microstructures, significantly increases the packing density of CNTs. This process enables directed transformation of vertical CNT microstructures into straight, inclined, and twisted shapes, which have robust mechanical properties exceeding those of typical microfabrication polymers. This in turn enables formation of nanocomposite CNT master molds by capillary-driven infiltration of polymers. The replica structures exhibit the anisotropic nanoscale texture of the aligned CNTs, and can have walls with sub-micron thickness and aspect ratios exceeding 50:1. Integration of CNT microstructures in fabrication offers further opportunity to exploit the electrical and thermal properties of CNTs, and diverse capabilities for chemical and biochemical functionalization 3.

We present methods for fabrication of patterned microstructures of vertically aligned carbon nanotubes (CNTs), and their use as master molds for production of polymer microstructures with organized nanoscale surface texture. The CNT forests are densified by condensation of solvent onto the substrate, which significantly increases their packing density and enables self-directed formation of 3D shapes.

制备，致密，副本三维碳纳米管微结构成型

The introduction of new materials and processes to microfabrication has, in large part, enabled many important advances in microsystems, lab-on-a-chip ...

科研

工程学

Fabricating Nanogaps by Nanoskiving

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two electrodes-and generating them in practical quantities-is still challenging. The preparation of nanogap electrodes using nanoskiving, which is a form of edge lithography, is a fast, simple and powerful technique. This method is an entirely mechanical process which does not include any photo- or electron-beam lithographic steps and does not require any special equipment or infrastructure such as clean rooms. Nanoskiving is used to fabricate electrically addressable nanogaps with control over all three dimensions; the smallest dimension of these structures is defined by the thickness of the sacrificial layer (Al or Ag) or self-assembled monolayers. These wires can be manually positioned by transporting them on drops of water and are directly electrically-addressable; no further lithography is required to connect them to an electrometer.

The fabrication of electrically addressable, high-aspect-ratio (> 1000:1) metal nanowires separated by gaps of single nanometers using either sacrificial layers of aluminum and silver or self-assembled monolayers as templates is described. These nanogap structures are fabricated without a clean room or any photo- or electron-beam lithographic processes by a form of edge lithography known as nanoskiving.

制造由Nanoskiving Nanogaps的

There are several methods of fabricating nanogaps with controlled spacings, but the precise control over the sub-nanometer spacing between two ...

化学

Dry Oxidation and Vacuum Annealing Treatments for Tuning the Wetting Properties of Carbon Nanotube Arrays

In this article, we describe a simple method to reversibly tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays. Here, CNT arrays are defined as densely packed multi-walled carbon nanotubes oriented perpendicular to the growth substrate as a result of a growth process by the standard thermal chemical vapor deposition (CVD) technique.1,2 These CNT arrays are then exposed to vacuum annealing treatment to make them more hydrophobic or to dry oxidation treatment to render them more hydrophilic. The hydrophobic CNT arrays can be turned hydrophilic by exposing them to dry oxidation treatment, while the hydrophilic CNT arrays can be turned hydrophobic by exposing them to vacuum annealing treatment. Using a combination of both treatments, CNT arrays can be repeatedly switched between hydrophilic and hydrophobic.2 Therefore, such combination show a very high potential in many industrial and consumer applications, including drug delivery system and high power density supercapacitors.3-5
The key to vary the wettability of CNT arrays is to control the surface concentration of oxygen adsorbates. Basically oxygen adsorbates can be introduced by exposing the CNT arrays to any oxidation treatment. Here we use dry oxidation treatments, such as oxygen plasma and UV/ozone, to functionalize the surface of CNT with oxygenated functional groups. These oxygenated functional groups allow hydrogen bond between the surface of CNT and water molecules to form, rendering the CNT hydrophilic. To turn them hydrophobic, adsorbed oxygen must be removed from the surface of CNT. Here we employ vacuum annealing treatment to induce oxygen desorption process. CNT arrays with extremely low surface concentration of oxygen adsorbates exhibit a superhydrophobic behavior.

This article describes a simple method to fabricate vertically aligned carbon nanotube arrays by CVD and to subsequently tune their wetting properties by exposing them to vacuum annealing or dry oxidation treatment.

干式氧化及真空退火处理调整的润湿性能的碳纳米管阵列

In this article, we describe a simple method to reversibly  tune the wetting properties of vertically aligned carbon nanotube (CNT) arrays.  Here, CNT ...

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

In recent years &pi;-conjugated organic semiconductors have emerged as the active material in a number of diverse applications including large-area, low-cost displays, photovoltaics, printable and flexible electronics and organic spin valves. Organics allow (a) low-cost, low-temperature processing and (b) molecular-level design of electronic, optical and spin transport characteristics. Such features are not readily available for mainstream inorganic semiconductors, which have enabled organics to carve a niche in the silicon-dominated electronics market. The first generation of organic-based devices has focused on thin film geometries, grown by physical vapor deposition or solution processing. However, it has been realized that organic nanostructures can be used to enhance performance of above-mentioned applications and significant effort has been invested in exploring methods for organic nanostructure fabrication.	
A particularly interesting class of organic nanostructures is the one in which vertically oriented organic nanowires, nanorods or nanotubes are organized in a well-regimented, high-density array. Such structures are highly versatile and are ideal morphological architectures for various applications such as chemical sensors, split-dipole nanoantennas, photovoltaic devices with radially heterostructured "core-shell" nanowires, and memory devices with a cross-point geometry. Such architecture is generally realized by a template-directed approach. In the past this method has been used to grow metal and inorganic semiconductor nanowire arrays. More recently &pi;-conjugated polymer nanowires have been grown within nanoporous templates. However, these approaches have had limited success in growing nanowires of technologically important &pi;-conjugated small molecular weight organics, such as tris-8-hydroxyquinoline aluminum (Alq3), rubrene and methanofullerenes, which are commonly used in diverse areas including organic displays, photovoltaics, thin film transistors and spintronics.	
Recently we have been able to address the above-mentioned issue by employing a novel "centrifugation-assisted" approach. This method therefore broadens the spectrum of organic materials that can be patterned in a vertically ordered nanowire array. Due to the technological importance of Alq3, rubrene and methanofullerenes, our method can be used to explore how the nanostructuring of these materials affects the performance of aforementioned organic devices. The purpose of this article is to describe the technical details of the above-mentioned protocol, demonstrate how this process can be extended to grow small-molecular organic nanowires on arbitrary substrates and finally, to discuss the critical steps, limitations, possible modifications, trouble-shooting and future applications.

We report a simple method for fabricating an ultrahigh density array of vertically ordered small-molecular organic nanowires. This method allows for synthesis of complex heterostructured hybrid nanowire geometries, which can be inexpensively grown on arbitrary substrates. These structures have potential applications in organic electronics, optoelectronics, chemical sensing, photovoltaics and spintronics.

超高密度垂直对齐的任意基质的小分子有机纳米线阵列

In  recent years &pi;-conjugated  organic semiconductors have emerged as the active material in a number of  diverse applications including large-area, ...

Manufacturing of Three-dimensionally Microstructured Nanocomposites through Microfluidic Infiltration

Microstructured composite beams reinforced with complex three-dimensionally (3D) patterned nanocomposite microfilaments are fabricated via nanocomposite in&#64257;ltration of 3D interconnected microfluidic networks. The manufacturing of the reinforced beams begins with the fabrication of microfluidic networks, which involves layer-by-layer deposition of fugitive ink filaments using a dispensing robot, filling the empty space between filaments using a low viscosity resin, curing the resin and finally removing the ink.&#160;Self-supported 3D structures with other geometries and many layers (e.g.&#160;a few hundreds layers) could be built using this method. The resulting tubular micro&#64258;uidic networks are then infiltrated with thermosetting nanocomposite suspensions containing nanofillers (e.g.&#160;single-walled carbon nanotubes), and subsequently cured. The infiltration is done by applying a pressure gradient between two ends of the empty network (either by applying a vacuum or vacuum-assisted microinjection). Prior to the infiltration, the nanocomposite suspensions are prepared by dispersing nanofillers into polymer matrices using ultrasonication and three-roll mixing methods. The nanocomposites (i.e.&#160;materials infiltrated) are then solidified under UV exposure/heat cure, resulting in a 3D-reinforced composite structure. The technique presented here enables the design of functional nanocomposite macroscopic products for microengineering applications such as actuators and sensors.

Three-dimensional (3D) microstructured composite beams are fabricated through the directed and localized infiltration of nanocomposites into 3D porous microfluidic networks. The flexibility of this manufacturing method enables the utilization of different thermosetting materials and nanofillers in order to achieve a variety of functional 3D reinforced nanocomposite macroscopic products.

通过微流体渗透制备三维微结构纳米复合材料的制造

Microstructured composite beams reinforced with complex three-dimensionally (3D) patterned nanocomposite microfilaments are fabricated via nanocomposite ...

Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data.
Exceptionally flat, 5 cm diameter, 375 &#181;m thick Si wafers with about 1 &#181;m variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 &#176;C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

A method for permanently bonding two silicon wafers so as to realize a uniform enclosure is described. This includes wafer preparation, cleaning, RT bonding, and annealing processes. The resulting bonded wafers (cells) have uniformity of enclosure ~1%1,2. The resulting geometry allows for measurements of confined liquids and gasses.

通过硅直接晶圆粘接制造均匀纳米级腔

Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned ...

Fabrication of Carbon Nanotube High-Frequency Nanoelectronic Biosensor for Sensing in High Ionic Strength Solutions

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them good candidates for high sensitivity biosensors. When a charged molecule binds to such a sensor surface, it alters the carrier density5 in the sensor, resulting in changes in its DC conductance. However, in an ionic solution a charged surface also attracts counter-ions from the solution, forming an electrical double layer (EDL). This EDL effectively screens off the charge, and in physiologically relevant conditions ~100 millimolar (mM), the characteristic charge screening length (Debye length) is less than a nanometer (nm). Thus, in high ionic strength solutions, charge based (DC) detection is fundamentally impeded6-8.
We overcome charge screening effects by detecting molecular dipoles rather than charges at high frequency, by operating carbon nanotube field effect transistors as high frequency mixers9-11. At high frequencies, the AC drive force can no longer overcome the solution drag and the ions in solution do not have sufficient time to form the EDL. Further, frequency mixing technique allows us to operate at frequencies high enough to overcome ionic screening, and yet detect the sensing signals at lower frequencies11-12. Also, the high transconductance of SWNT transistors provides an internal gain for the sensing signal, which obviates the need for external signal amplifier.
Here, we describe the protocol to (a) fabricate SWNT transistors, (b) functionalize biomolecules to the nanotube13, (c) design and stamp a poly-dimethylsiloxane (PDMS) micro-fluidic chamber14 onto the device, and (d) carry out high frequency sensing in different ionic strength solutions11.

We describe the device fabrication and measurement protocol for carbon nanotube based high frequency biosensors. The high frequency sensing technique mitigates the fundamental ionic (Debye) screening effect and allows nanotube biosensor to be operated in high ionic strength solutions where conventional electronic biosensors fail. Our technology provides a unique platform for point-of-care (POC) electronic biosensors operating in physiologically relevant conditions.

制备碳纳米管高频纳电子生物传感器的传感高离子强度的解决方案

The unique electronic properties and high surface-to-volume ratios of single-walled carbon nanotubes (SWNT) and semiconductor nanowires (NW) 1-4 make them ...

生物工程

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of nanowires. DEP is used for nanowire analysis, characterization, and for solution-based fabrication of semiconducting devices. The method works by applying an alternating electric field between metallic electrodes. The nanowire formulation is then dropped onto the electrodes which are on an inclined surface to create a flow of the formulation using gravity. The nanowires then align along the gradient of the electric field and in the direction of the liquid flow. The frequency of the field can be adjusted to select nanowires with superior conductivity and lower trap density. 
In this work, flow-assisted DEP is used to create nanowire field effect transistors. Flow-assisted DEP has several advantages: it allows selection of nanowire electrical properties; control of nanowire length; placement of nanowires in specific areas; control of orientation of nanowires; and control of nanowire density in the device. 
The technique can be expanded to many other applications such as gas sensors and microwave switches. The technique is efficient, quick, reproducible, and it uses a minimal amount of dilute solution making it ideal for the testing of novel nanomaterials. Wafer scale assembly of nanowire devices can also be achieved using this technique, allowing large numbers of samples for testing and large-area electronic applications.

In this paper, flow assisted dielectrophoresis is demonstrated for the self-assembly of nanowire devices. The fabrication of a silicon nanowire field effect transistor is shown as an example.

流动辅助介: 一种低成本的制备高性能溶液可纳米线器件的方法

Flow-assisted dielectrophoresis (DEP) is an efficient self-assembly method for the controllable and reproducible positioning, alignment, and selection of ...

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D materials is still in nascent stages, scientists cannot fully rely on traditional semiconductor techniques for related research. Delicate processes from locating the materials to electrode definition need to be well controlled. In this article, a universal fabrication protocol required in manufacturing nanoscale electronics, such as 2D quasi-heterojunction bipolar transistors (Q-HBT), and 2D back-gated transistors are demonstrated. This protocol includes the determination of material position, electron beam lithography (EBL), metal electrode definition, et al. A step by step narrative of the fabrication procedures for these devices are also presented. Furthermore, results show that each of the fabricated devices has achieved high performance with high repeatability. This work reveals a comprehensive description of process flow for preparing 2D nano-electronics, enables the research groups to access this information, and pave the way toward future electronics.

The article aims to introduce a standard and reliable fabrication procedure for the development of future low dimensional nanoelectronics.

制造二维电子学的标准可靠方法

Two-dimensional (2D) materials have attracted huge attention due to their unique properties and potential applications. Since wafer scale synthesis of 2D ...

Fabrication of Micro-Patterned Chip with Controlled Thickness for High-Throughput Cryogenic Electron Microscopy

A major limitation for the efficient and high-throughput structure analysis of biomolecules using cryogenic electron microscopy (cryo-EM) is the difficulty of preparing cryo-EM samples with controlled ice thickness at the nanoscale. The silicon (Si)-based chip, which has a regular array of micro-holes with graphene oxide (GO) window patterned on a thickness-controlled silicon nitride (SixNy) film, has been developed by applying microelectromechanical system (MEMS) techniques. UV photolithography, chemical vapor deposition, wet and dry etching of the thin film, and drop-casting of 2D nanosheet materials were used for mass-production of the micro-patterned chips with GO windows. The depth of the micro-holes is regulated to control the ice thickness on-demand, depending on the size of the specimen for cryo-EM analysis. The favorable affinity of GO toward biomolecules concentrates the biomolecules of interest within the micro-hole during cryo-EM sample preparation. The micro-patterned chip with GO windows enables high-throughput cryo-EM imaging of various biological molecules, as well as inorganic nanomaterials.

A newly developed micro-patterned chip with graphene oxide windows is fabricated by applying microelectromechanical system techniques, enabling efficient and high-throughput cryogenic electron microscopy imaging of various biomolecules and nanomaterials.